Designing With the SN54/74LS123
SDLA006A March 1997
1
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright 1997, Texas Instruments Incorporated
2
Contents Title
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Rules for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Output Pulse Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Output Pulse Duration Versus Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Special Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Device-to-Device Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 74LS123N/J Device-to-Device Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delayed-Pulse Generator With Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Missing-Pulse Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Negative/Positive Edge-Triggered One-Shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse-Duration Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Discriminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 10 11 12 13 14 15
List of Illustrations Figure
Title
Page
1
’LS123 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Remote Trimming Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3
Retrigger Pulse-Duration Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4
Multiplier Factor Versus External Capacitor (Cext) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5
Output Pulse Duration Versus External Timing Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Output Pulse Duration Versus Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Average Percent Change Versus Pulse-Duration Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
Pulse-Duration Variation Versus Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
9
Pulse-Duration Variation Versus Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
10
Multiplier Factor Versus Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
11
Delayed-Pulse Generator With Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12
Missing-Pulse Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13
Low-Power Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
14
Negative/Positive Edge-Triggered One-Shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15
Pulse-Duration Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16
Frequency-Discriminator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
17
’LS123 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
iii
iv
Introduction The Texas Instruments (TI) SN54/74LS123 dual retriggerable monostable multivibrator is a one-shot device capable of very long output pulses and up to 100% duty cycle. The ’LS123 also features dc triggering from gated low-level active A and high-level active B inputs and provides a clear input that terminates the output pulse of any predetermined time independent of timing components, Rext and Cext. The output pulse duration can also be extended by retriggering the input prior to the termination of an existing output pulse. Retrigger pulses starting before 0.22 Cext (in pF) ns after the initial trigger pulse will be ignored and the output duration will remain unchanged. The B input on an ’LS123 is designed to handle pulses with a transition rate as slow as 0.1 mV/ns, (Schmitt-trigger input) with jitter-free one-shot action. This capability allows the ’LS123 to be used as an interface element between circuits with very slow-rising output pulses and circuits that require fast-rising input pulses.
Features
• • • • •
100% maximum duty cycle Dc triggered from active-high or active-low logic inputs Input clamp diodes Low power dissipation Compensated for VCC and temperature variations
Figure 1 is a functional block diagram of the ’LS123. Each one-shot has two inputs, one active-low and one active-high, which allow both leading or trailing edge triggering. When triggered, the basic pulse duration can be extended by retriggering the gated low-level active A or high-level active B inputs, or the pulse duration can be reduced by use of the overriding clear. Therefore, an input cycle time shorter than the output cycle time will retrigger the ’LS123 and result in a continuously high Q output. VCC Cext 1A
VCC
Rext
1 14
2 1B 3 1CLR
2A
15 13
R
4
Rext
Cext
1Q
9 6
10 2B 11 2CLR
1Q
7 5
R
12
2Q 2Q
Figure 1. ’LS123 Logic Diagram
1
FUNCTION TABLE CLEAR
A INPUT
B INPUT
Q
Q
L
X
X
X
H
X
L L†
H H†
X
X
L
L†
H†
H
L
↑
H
↓
H
LHL‡ LHL‡
HLH§ HLH§
↑
L
H LHL‡ HLH§ † These lines of the functional tables assume that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the setup. ‡ This is a low-to-high-to-low pulse. § This is a high-to-low-to-high pulse.
Rules for Operation 1.
An external resistor (Rext) and an external capacitor (Cext) are required, as shown in Figure 1, for proper circuit operation.
NOTE: For best results, system ground should be applied to the Cext terminals. 2. 3. 4. 5. 6.
This value of Rext may vary from 5 kΩ to 180 kΩ between –55°C and 125°C. Cext may vary from 0 pF to any necessary value. The input may have a minimum amplitude of –0.5 V and a maximum of 5.5 V. When an electrolytic capacitor is used as Cext, the switching diode required by most one-shots is not needed for ’LS123 operation. For remote trimming, the circuit shown in Figure 2 is recommended. Rext Pins 7 and/or 15 Cext
RRM
Pins 6 and/or 14 VCC NOTE: RRM is placed as close as possible to the ’LS123.
Figure 2. Remote Trimming Circuit 7.
The retrigger pulse duration is calculated as shown in Figure 3.
tRT
tRT = tW + tPLH = K • Rext • Cext + tPHL
Figure 3. Retrigger Pulse-Duration Calculation
2
8.
A 0.001-µF to 0.1-µF bypass capacitor between VCC and GND as close as possible to the ’LS123 is recommended (see Figure 4). 1 µF
External Capacitor – C
’LS123 PW = KRC (K is independent of R) 0.1 µf
0.01 µf
0.001 µf
100 pF 0.30
0.35
0.40
0.45
0.50
0.55
Multiplier Factor – K
Figure 4. Multiplier Factor Versus External Capacitor (Cext) Output Pulse Duration The basic output pulse duration is essentially determined by the values of external capacitance and timing resistance. For pulse durations when Cext is < 1 µF, use the following formula: tw
+ K@R @C t
ext
(also see Figure 5)
(1)
When Cext is > 1 µF, the output pulse duration is defined as: tw
+ 0.33 @ R @ C t
ext
(2)
Where, for the two previous equations, as applicable: K Rt Cext tw
= multiplier factor = given in kΩ (Internal or External Timing Resistance) = in pF = in ns
For capacitor values of less than 1000 pF, the typical curves in Figure 5 can be used.
3
t w – Output Pulse Duration – ns
100,000
Rt = 200 kΩ† Rt = 160 kΩ Rt = 80 kΩ
10,000
1,000
100 Rt = 40 kΩ Rt = 20 kΩ Rt = 10 kΩ Rt = 5 kΩ
10 1
10
100
1000
Cext – External Timing Capacitance – pF † This value of resistance exceeds the maximum recommended for use over the full temperature range of the SN54LS circuits.
Figure 5. Output Pulse Duration Versus External Timing Capacitance Output Pulse Duration Versus Supply Voltage Figure 6 shows the relationship between the output pulse duration and VCC at specific temperatures.
t w – Output Pulse Duration – ns
5.2 ’LS123, R = 30.1 kΩ, C = 200 pF
4.0 –55°C 3.8 0°C 3.6 25°C 3.4
70°C 125°C
3.2
3.0 4.5
4.75
5
5.25
5.5
5.75
VCC – Supply Voltage – V
Figure 6. Output Pulse Duration Versus Supply Voltage
4
Special Considerations Because these monostable multivibrators are half analog and half digital, they inherently are more sensitive to noise on the analog portion (timing leads) than standard digital circuits. They should not be located near noise-producing souces or transient-carrying conductors and liberal power-supply bypassing is recommended for greater reliability and repeatibility. Also, a monostable should not be used as a fix for asynchronous systems; synchronous design techniques always provide better performance. For time delays over 1.5 s or timing capacitors over 100 µF, it is usually better to use a free-running astable multivibrator and a couple of inexpensive decade counters (such as a 7490A) to generate the equivalent of a long-delay one-shot. Astable oscillators made with monostable building blocks have stabilities approaching five parts in 100 and should not be used if system timing is critical. Crystal oscillators provide better stability. In all one-shot applications, follow these guidelines:
• • •
•
•
Use good high-frequency 0.1-µF (ceramic disk) capacitors, located 1 to 2 inches from the monostable package, to bypass VCC to ground. Keep timing components (Rt, Ct) close to the package and away from high transient voltage or current-carrying conductors. Keep the Q-output trace away from the CLR lead; the negative-going edge when the one-shot times out may cause the C lead to be pulled down, which may restart the cycle. If this happens, constantly high (Q = H, Q = L) outputs with 50-ns low spikes will occur at the repetition rate determined by Rt and Ct. If sufficient trace isolation cannot be obtained, a 50-pF capacitor bypassing the C lead to ground usually eliminates the problem. Beware of using the diode or transistor protective arrangement when retriggerable operation is required; the second output pulse may be shorter due to excess charge left on the capacitor. This may result in early time out and apparent failure of retriggerable operation. Use a good capacitor, one that is able to withstand 1 V in reverse and meet the leakage current requirements of the particular one-shot. Remember that the timing equation associated with each device has a prediction accuracy. Generally, for applications requiring better than ±10% accuracy, trimming to pulse duration is necessary.
Variations in performance versus applicable parameters are shown in Figures 7 through 10. 6 Rext = 5 kΩ Rext = 80 kΩ Rext = 160 kΩ
Average Percent Change – %
5
4 3 2
1
0 –1 10 p
100 p 300 p 500 p
1n
2n
5n
1µ
10 µ
50 µ
100 µ 500 µ
tw – Pulse-Duration Tolerance – s
Figure 7. Average Percent Change Versus Pulse-Duration Tolerance
5
3
t w – Pulse-Duration Variation – %
2 1 0 –1 –2 –3 –4 –5 4.5
4.7
4.9
5.1
5.3
5.5
VCC – Supply Voltage – V
Figure 8. Pulse-Duration Variation Versus Supply Voltage
3
t w – Pulse-Duration Variation – %
2 1 0 –1 –2 –3 –4 –5
0
20
40
60
TA – Free-Air Temperature – °C
Figure 9. Pulse-Duration Variation Versus Free-Air Temperature
6
0.51 0.50 0.49 0.48 0.47
K – Multiplier Factor
0.46 0.45 0.44 0.43 0.42 0.41 0.40 0.39 0.38 0.37 0.36 0.35 0.34 0.33 0.32 0.31 10 p
100 p 300 p 500 p 1 n
2n
5n
1µ
10 µ
50 µ 100 µ
500 µ
C – Capacitance – F
Figure 10. Multiplier Factor Versus Capacitance Device-to-Device Variation Device-to-device variation is always a concern with designers when using a part such as the ’LS123. The data in Table 1 were taken in the laboratory using three external-resistor (Rext) values. Ten devices were tested, using three different date codes, and using 12 different external capacitor (Cext) values. Each column was averaged and that number considered a target value, and the high and low values considered the + and – percentage change from that value. These results indicate that the average percentage change from the target value probably should not exceed ±5%. This should not, however, be interpreted as an ensured parameter. This parameter is not tested by TI.
7
Table 1. 74LS123N/J Device-to-Device Variation Example 1. Conditions: TA = 25°C, Ten units, Rext = 5 kΩ (4.96 kΩ), Capacitances (as listed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ms Cext
1 µF
10 µF
50 µF
100 µF
500 µF
8400
1.88
19.8
95.4
213
851
8500
1.94
20.2
97.2
217
866
3450
8400
1.86
19.7
95.2
213
848
3500
8600
1.88
20
96.6
216
860
2100
3450
8400
1.88
19.9
95.8
214
853
2100
3450
8500
1.9
20
96.4
215
856
970
2100
3450
8400
1.87
19.6
95.2
213
850
615
940
2100
3450
8500
1.95
20.4
97.7
218
867
615
960
2100
3400
8300
1.82
19.3
93.2
209
830 859
10 pF
100 pF
300 pF
500 pF
1000 pF
2000 pF
1.
80
250
615
960
2100
3450
2.
83
255
615
960
2100
3400
3.
84
255
625
970
2150
4.
88
260
630
980
2150
5.
88
255
620
970
6.
86
260
620
970
7.
82
255
620
8.
83
260
9.
82
250
5000 pF
UNIT
87
260
630
980
2150
3500
8500
1.89
20
96.5
216
AVG
10.
83.7
255
620.5
965
2115
3450
8450
1.888
19.89
95.92
214.4
854
MAX
88
260
630
980
2150
3500
8600
1.95
20.4
97.7
218
867
MIN
80
250
615
940
2100
3400
8300
1.82
19.3
93.2
209
830
%CHG+
5.14
1.96
1.53
1.55
1.65
1.45
1.78
3.28
2.56
1.86
1.68
1.52
%CHG–
4.12
1.96
0.89
2.59
0.71
1.45
1.78
3.60
2.97
2.84
2.25
2.81
Example 2. Conditions: TA = 25°C, Ten units, Rext = 80 kΩ (80.2 kΩ), Capacitances (as listed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . µs . . . . . . . . . . . . . . . . . . . . . . X . . . . . . . . . . . ms . . . . . . . . . . X . . . . . . s . . . . . . X Cext
10 pF
100 pF
300 pF
500 pF
1. 0.91
3.9
10
2. 0.92
3.9
10
3. 0.9
3.9
4. 0.94
3.95
5. 0.89 6. 0.915
1 µF
10 µF
50 µF
100 µF
500 µF
325
1.61
3.54
14.7
334
1.64
3.59
14.9
1000 pF
2000 pF
5000 pF
16
33.5
53.5
140
34
16
33.5
58.5
141
35
10.1
16.2
34
59
141
34
329
1.62
3.56
14.8
10.3
16.4
34.5
60
143
34.5
334
1.64
3.61
15
3.9
10
16.1
34
58.5
141
34.5
331
1.62
3.57
14.8
3.9
10.1
16.2
34
59
142
34.5
333
1.63
3.59
14.9
7. 0.92
3.9
10.1
16.2
34
58.5
140
34
328
1.61
3.54
14.7
8. 0.91
3.9
10
15.9
33.5
58.5
141
35
328
1.65
3.62
15
9. 0.87
3.8
10
15.9
33.5
58
138
33.5
322
1.58
3.48
14.4
10. 0.91
3.9
10.2
16.3
34.5
59.5
143
34.5
334
1.64
3.61
15
UNIT
AVG
0.9085
3.895
10.08
16.12
33.9
58.8
141
34.35
331.1
1.624
3.571
14.82
MAX
0.94
3.95
10.3
16.4
34.5
60
143
35
338
1.65
3.62
15
MIN
0.87
3.8
10
15.9
33.5
58
138
33.5
322
1.58
3.48
14.4
%CHG+
3.47
1.41
2.18
1.74
1.77
2.04
1.42
1.89
2.08
1.60
1.37
1.21
%CHG–
4.24
2.44
0.79
1.36
1.18
1.36
2.13
2.47
2.75
2.71
2.55
2.83
8
Table 1. 74LS123N/J Device-to-Device Variation (Continued) Example 3. Conditions: TA = 25°C, Ten units, Rext = 160 kΩ (159.7 kΩ), Capacitances (as listed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X ms X . . . . . . . . . . . . . . . . . s . . . . . . X Cext
10 pF
100 pF
300 pF
500 pF
1000 pF
2000 pF
5000 pF
1 µF
10 µF
50 µF
100 µF
500 µF
UNIT 1.
1.79
7.8
20
32
67
117
280
68.9
658
3.23
7.1
29.6
2.
1.8
7.8
20
32
67
118
280
70.5
672
3.29
7.21
30
3.
1.78
7.8
20
32.5
68
119
280
69.5
662
3.25
7.16
29.8
4.
1.85
7.9
20.5
33
69
120
285
70.4
672
3.3
7.26
30.2
5.
1.76
7.75
20
32
67.5
118
285
70
667
3.27
7.17
29.9
6.
1.8
7.8
20
32.5
68
119
285
70.4
670
3.28
7.21
30.1
7.
1.8
7.85
20
32.5
67.5
118
280
68.9
658
3.23
7.12
29.6
8.
1.79
7.8
20
32
66.5
118
285
71.5
678
3.31
7.26
30.2
9.
1.71
7.55
20
32
66.5
116
275
67.9
648
3.19
7
29.2
10.
30.2
1.78
7.8
20.5
33
68.5
120
285
70.5
672
3.3
7.26
AVG
1.786
7.785
20.1
32.35
67.55
118.3
282
69.86
665.7
3.265
7.175
29.88
MAX
1.85
7.9
20.5
33
69
120
285
71.5
678
3.31
7.26
30.2
MIN
1.71
7.55
20
32
66.5
116
275
67.9
648
3.19
7
29.2
%CHG+
3.58
1.48
1.99
2.01
2.15
1.44
1.06
2.35
1.85
1.38
1.18
1.07
%CHG–
4.26
3.02
0.5
1.08
1.55
1.94
2.48
2.81
2.66
2.30
2.44
2.28
9
Applications Delayed-Pulse Generator With Override In Figure 11, the first one-shot (OS1) determines the delay time by preselected values of Rext1 and Cext1. The second one-shot (OS2) determines the output pulse duration by preselected values of Rext and Cext. The output pulse can be terminated at any time by a positive rising pulse into the override input. VCC
Rext1
Rext2
Cext1
Cext2
1A 1B 1CLR
Input
Q 1/2 ’LS123 OS1 1CLR
2A 2B 2CLR
Output
Q 1/2 ’LS123 OS2 2CLR
Override Input 1/6 ’LS04
Input
1 0
Output OS1
1 0 1
Delayed OS2 0
Figure 11. Delayed-Pulse Generator with Override
10
Missing-Pulse Detector The pulse duration of OS1, determined by Cext1 and Rext1, is set to at least one half the incoming pulse period. The rise of the incoming pulse fires OS1, producing a high on the Q output. The output of OS1 remains high as long as there is no missing pulse in the pulse train. Therefore, the one-shot is being retriggered. However, if a pulse is missing from the pulse train, the output of OS1 falls and OS2 fires. VCC
Rext1
Rext2
Cext1
Cext2
1A 1B 1CLR
Input VCC
Q 1/2 ’LS123 OS 1 1CLR
2A 2B 2CLR
Q 1/2 ’LS123 OS2 2CLR
Output
VCC
1
Input
0 1
Output OS1
0 1
Output OS2
0
Figure 12. Missing-Pulse Detector
11
Low-Power Pulse Generator The output frequency developed by the OS1 configuration is determined by Rext1 and Cext1, while the output pulse duration of OS2 is determined by Rext2 and Cext2. A low-power pulse generator is shown in Figure 13. VCC
Rext1 Cext1
Rext2 Cext2
2A
1A 1B 1CLR
2B 2CLR
Q 1/2 ’LS123 OS1 1CLR Q
VCC
Output OS1
Q 1/2 ’LS123 OS2 1 Q 2CLR 1CLR
VCC
1
1. Duty cycle of output pulse
0
2. f
1 Output OS2 0
+K R
1 ext1
C ext1
+ RR
ext2
C ext2 1 ext C ext1
MHz
where Rext is in kΩ and Cext in pF. NOTE: See Figure 4 or 10, as appropriate, for values of K.
Figure 13. Low-Power Pulse Generator
12
Outputs
Negative/Positive Edge-Triggered One-Shot Monostable multivibrators OS1 and OS2 arranged in a circuit such that a negative-going input pulse or a positive-going input pulse causes OS1 (OS2 disabled) to change states (see Figure 14). The outputs of OS1 and OS2 are connected to an OR gate, which outputs a pulse when OS1 or OS2 switches. This circuit can also be utilized as a frequency doubler. VCC Rext1 Cext1 1A 1B 1CLR
Q 1/2 ’LS123 OS1 Q 1CLR
Output
VCC Rext2
1/4 74LS32
Cext2 Input
2A 2B 2CLR
Q 1/2 ’LS123 OS2 1 Q 2CLR 1CLR
Figure 14. Negative/Positive Edge-Triggered One-Shot
13
Pulse-Duration Detector The circuit shown in Figure 15 generates an output pulse (t3) only if the trigger pulse duration (t2) is wider than the programmed pulse (tw = K • Rext • Cext) of the ’LS123. Q1 is normally off and the A input of the ’LS123 is approximately VCC. The normal Q output of the ’LS123 is low and the Q2 output is off (the output is normally low because no pullup exists). A trigger of duration t1 applied at the input is differentiated by the R1C1 combination and turns Q1 on. The result of that momentary condition at the base of Q1 is a negative-going pulse at point 1 (the A input of the ’LS123), which triggers ’LS123. The ’LS123 remains on for the time tw = K • Rext • Cext, which is waveform t2. The output of the ’LS123 turns on Q2 for a time equal to t2. At the end of t2, Q2 turns off. If the input pulse is still high, it appears at the output. The circuit output pulse duration (t3) equals the input pulse duration minus the pulse duration of the ’LS123. VCC
VCC
47 kΩ
Rext1
10 kΩ
Cext1 “A” or 1
1A
C1 0.001 µF Input
Output
1B 1CLR
Q1 R1 10 kΩ
Q 1/2 ’LS123 OS1 1CLR
Q2
VCC
t1 1
Input
0
VCC
’LS123 Output
1 t2 VOH t3
Output
Figure 15. Pulse-Duration Detector
14
Frequency Discriminator In Figure 16, R1 and C1 form a resistor-capacitor integration network that produces a linear output-voltage curve proportional to frequency over a limited range. VCC Rext1 Cext1 1A 1B 1CLR
Input
R1 Q 1/2 ’LS123 OS1 1CLR
Output C1
VCC 1 Input
Output
0 VOH 0
Figure 16. Frequency-Discriminator Circuit
15
16 R ext /C ext 1
7
15
A Input 9
2 E Input
5
10
Q Ouput 13
3 CLR 11
4 Q Ouput 12 6 C ext 14
NOTE: For clarity, only one-half of the device is shown.
Figure 17. ’LS123 Schematic
