Design of DC-DC Converters - IEEE Entity Web Hosting

Design of DC-DC Converters Frank Xi [email protected]

Monolithic Power Systems Inc. IEEE SSCS Dallas Chapter, October 2007

Design of DC-DC Converters

DC-DC Converter Basics

Topology and Operation of DCDC Converters Control Scheme for DCDC

DC-DC Converter Design Techniques

System Level Modeling and Design Building Block Design Considerations

11/1/2007

IEEE SSCS - Oct. 2007

2


DC-DC Converter is a Voltage Regulator

Use Switches, Inductor and Capacitor for Power Conversion Switched Mode Operation

Why DC-DC Converters?

High Efficiency Can Step-Down, Step-up, or Both, or Invert Can Achieve Higher Output Power

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Why not DC-DC Converters?

Complex Control Loop Higher Noise and Output Ripple More External Components

Basic DC-DC Converter Topologies

Majority of DC-DC uses PWM Control Operated in CCM Mode

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4


Step-down (Buck) VIN IIN

VSW S

D

IO

VOUT

IL

ID

VSW

L

IC

Basic Relationships

C

T

VOUT IL

TON

TON VIN = D ⋅VIN T = D ⋅ I OUT

VOUT =

IO IIN

CCM Mode IL always supplies load IC small, independent of load I IN

ID

Continuous Conduction Mode (CCM) IL

DCM Mode 2

VOUT

IO Discontinuous Conduction Mode (DCM)

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TON V = 2 I O ⋅ L ⋅ T IN 2 TON + VIN


5


Step-up (Boost) L

VIN

VSW

D

IO

VOUT

IL

IC S

C

Basic Relationships

VSW T

VOUT

TON

IL

TOFF

CCM Mode IL only supplies load during TOFF period IC large and load dependent VOUT =

T TOFF

I IN = I L =

IC

-IO Continuous Conduction Mode (CCM)

VIN =

1 ⋅ VIN 1− D

1 ⋅ I OUT 1− D

DCM Mode

IL

2IO ⋅ L ⋅ T VIN VIN 2 TON

TON + 2

IC

VOUT =

-IO Discontinuous Conduction Mode (DCM)

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6

Common Control Architectures

Modulation Scheme

PFM (Pulse-Frequency-Modulation)

Pulse Skipping, Hysteretic, Constant-on etc. High Efficiency at Light Load Inherently Higher Output Ripple Unmanaged Spectrum Noise

PWM (Pulse-Width-Modulation)

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Fixed Frequency with Variable Duty Cycle Better Transient Response (except Hysteretic?) Most Widely Used IEEE SSCS - Oct. 2007

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Control Method (for PWM)

Voltage Mode

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Regulates Output Voltage by Adjusting Duty Cycle Constant Ramp for Modulation, Better Noise Immunity LC Filter Contributes to Complex Conjugate Poles Loop Has No Information on Inductor Current Slower Response to Input Voltage Change Bandwidth Varies with Input Voltage Current Limit Done Separately IEEE SSCS - Oct. 2007

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Current Mode

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PCM (Peak-Current-Mode) Most Commonly Used Regulates Inductor Current to Satisfy Load Demand and Maintain Output Voltage Fast Current Loop makes Inductor to be a VCCS, eliminates Complex Conjugate Poles Easy Built-in Cycle-to-Cycle Current Limit Naturally Suitable for Multi-Phase Operation Current Sense Susceptible to Noise Need Slope Compensation for >50% Duty Cycle Operation IEEE SSCS - Oct. 2007

9

DC-DC Converter Design

Examples of Common DC-DC Converters VIN

Voltage Mode Buck

S1

L

VSW

VOUT R1

RESR

CLK

RL S2

D’

VRAMP

R2

C

VEA

VSW VOUT D

Q

S

QB R

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CLK RST

VRAMP VEA

IL

IOUT

VFB EA

VREF


10

Voltage Mode Buck Voltage Mode Buck Transfer Functions: vO (1 + sCRESR ) (1 + sCRESR ) ≈ VIN = VIN 2 L s s d 2 s LC + s ( + CRESR ) + 1 + 1+ RL Qω0 ω0 2

ω0 =

1 ,Q = LC 1 RL

1 L C + RESR L C

and d 1 = a( s) vFB VR where a ( s ) is the transfer function of the error amplifier

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11

Voltage Mode Buck Control (Duty Cycle) to Output Transfer Function: Example: L=2.2uH, C=22uF, RESR=10m Ohm VIN=5V, VOUT=3.3V RL=10 Ohm FSW=1.5MHz VRAMP=100mV ω0 = 22.9kHz Q = ~15.8 ωZ = 700kHz

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Voltage Mode Buck - Error Amp Ex. 1 Use low DC gain to set the bandwidth so that the phase margin is acceptable: R1

R2 VEA

VFB

Bandwidth: ~400kHz Phase margin: ~35° Conditionally stable

EA VREF

VEA = VREF + vEA = − LG = −

R2 (VREF − VFB ) R1

R2 vFB R1 R2 VIN (1 + sCRESR ) ⋅ s s2 R1 VR 1+ + 2 Qω0 ω0

Closed loop step response

Example: R2=500k, R1=100k, VR=100mV 11/1/2007


13

Voltage Mode Buck - Error Amp Ex. 1 Some Improvements Can Be Added:

Make VRAMP proportional to VIN -> Constant Bandwidth Add Feed-forward Cap on Feedback Resistor String -> better phase margin

Limitations of Low DC Gain:

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Loose Output Regulation Need some ESR to Stabilize the Loop Small Modulation Ramp Sensitive to Noise DC Offset if Output Cap has large ESR


14

Voltage Mode Buck - Error Amp Ex. 2 Use Type-III Compensation Network to Re-Shape Loop Frequency Response:

Example Design Steps: C C R 1. Set R1C2=100uS for desired BW of ~300kHz V C R R 2. Set 1st zero to be 1/5 of ω0: R1=1Meg, C1=30pF, ωz1=5.3kHz EA V V 3. Set 2nd zero to be 4x of ω0: C2=10pF, R3=200k, (1 + sC R )[1 + s ( R + R )C ] v ≈ −A ωz2=79.5kHz [1 + sR (1 + A )(C + C )](1 + sR C )(1 + sR C || C ) v 4. mid-band DC gain of 5: (1 + sC R )(1 + sR C ) V (1 + sCR ) ⋅ LG ≈ − A s s [1 + sR A C ](1 + sR C )(1 + sR C ) V + 1+ R3=200k ω Q ω 5. Set 2nd and 3rd pole to near 1 V ⋅ UGBW ≈ R C ⋅ V LC switching frequency for • High DC gain rolls off by dominant pole and, high frequency noise st phase shift recovered by 1 zero before ω0 attenuation: nd • 2 zero brings back phase shift above ω0 C3=0.2pF, ωp2=795kHz; • 2nd and 3rd pole attenuates high frequency noise R2=10k, ωp3=1.5MHz 3

2

2

FB

3

1

1

EA

REF

1 1

EA

3

2

2

0

3

FB

0

1

3

1 1

2

3

2

2

1

3

1

IN

ESR

0

2

3

0

1

2

2

1

3

R

2

0

0

IN

1

2

R

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15

Voltage Mode Buck - Error Amp Ex. 2

• Modulation ramp VRAMP increased to

500mV for better noise immunity • Blue: control to output transfer function • Green: Type-III compensation error Amp transfer function • Red: Complete loop transfer function bandwidth: ~340kHz, PM: ~65 degree 11/1/2007

Compare to Error Amp Ex. 1: • Step response has less overshoot due to better phase margin • Settling is much slower due to 1st zero at low frequency


16


VIN

Current Mode Buck (Peak Current Control) S1

L

VSW

VOUT R1

RESR

CLK

RL S2

D’

R2

C

VRAMP

VEA

RST RSEN

VSW VOUT

Slope Comp D

Q

S

QB R

IL

CLK RST

VRAMP VEA

IOUT

VFB EA VREF

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Current Mode Buck Inductor Current Instability for Duty Cycle > 50%: ⎛ m ⎞ m ie [n + 1] = ie [n] ⋅ (− 2 ) = ie [0] ⋅ ⎜⎜ − 2 ⎟⎟ m1 ⎝ m1 ⎠

1. D=1/3: m2/m1=1/2 ie[n]

m1

m2 ie[n+1]

m2

m1 ie[n+1]

3. D=2/3 with slope compensation ma

m2 < 1 : ie attenuates over cycles m1 m2 > 1 : ie grows over cycles m1

2. D=2/3: m2/m1=2 ie[n]

Requires Slope Compensation: ie [n + 1] = ie [n] ⋅ (−

ie[n]

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m2 − ma ) m1 + ma

ma is chosen so that ie[n+1]

n

m2 − ma <1 m1 + ma

m2 , guaranteed stable 2 ma = m2 , 1 cycle correction

ex : ma =


18

Current Mode Buck • Fast current loop regulates inductor peak current, can be modeled as a VCCS with output impedance Rx • Slower voltage loop provides reference for current loop Gm =

RX VIN

Gm

IO

VOUT R1

RESR RL

io 1 1 1 1 = = R T m vEA RSEN 1 + L S [(1 + a )(1 − D ) − 0.5] RSEN 1 + RL L m1 RX

where RX =

Switched Operation results in delay and sampling effect : H e (s) =

R2

C

VEA

1 + α 1 − e − sTS 1 + α ⋅ e − sTS sTS

Gm ( s ) ≈

EA VREF

Q=

1

m2 − ma m1 + ma

RSEN 1 RSEN

2

1 1 + α 1 − e − sTS − sTS RT m sTS 1 + L S [(1 + a )(1 − D ) − 0.5] 1 + α ⋅ e L m1 1 1 RL s s2 1+ + 2 1+ RX QωS ωS 1

π (1 + ma )(1 − D) − 0.5 m1

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where α =

Complete VCCS transconductance including frequency response : Gm ( s ) =

VFB

L ma TS [(1 + )(1 − D) − 0.5] m1


=

2

1

π 1 − 2 D(1 − ma ) m2

19

Current Mode Buck Peak Current Mode Current Loop Transfer Function Example: L=2.2uH, VIN=5V, VOUT=3.3V, RL=10 Ohm RSEN = 0.5 Ohm FSW = 1.5MHz Blue: ma=0.5*m2 RX=19.4 Ohm Gm=1.32 A/V Q=1.87 Green: ma=m2 RX=6.6 Ohm Gm=0.80 A/V Q=0.64

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Current Mode Buck Control to Output Transfer Function Equivalently Single-Pole System with Current Source Input vo R 1 1 1 + sCRESR = Gm ⋅ Z O = L vEA RSEN 1 + RL 1 + s + ( s ) 2 [1 + sC ( RL || RX )] RX Qω S ωS

Example: C=22uF, RESR=10m Ohm RSEN = 0.5 Ohm FSW = 1.5MHz RX=19.4 Ohm RL=10k, 1k, 100, 10, 1 Ohm

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RL=10k, 1k, 100, 10, 1 Ohm

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Current Mode Buck – Error Amp Error Amplifier Example: C1

a( s) = CC

RZ

vEA 1 + sCC RZ ≈ − A0 vFB [1 + sCC (ro + g m R1ro + RZ )](1 + sC1RZ )

(CC >> C1 ) where : g m is the transconductance of the error amp ro is the output impedance

R1 VFB

ie

EA

VEA

VREF

• Bandwidth defined by R1 and C1 • Much smaller CC, need large RZ • VFB more error during transient Example: gm=100uS, ro=10MOhm, R1=100kOhm, CC=25pF, RZ=1.5MOhm, C1=0.3pF 11/1/2007


22

Current Mode Buck – Error Amp Complete Loop Transfer Function of Current Mode Buck: LG = −

RL 1 1 1 + sCRESR 1 + sCC RZ ⋅ ⋅ A0 RSEN 1 + RL 1 + s + ( s ) 2 [1 + sC ( RL || RX )] [1 + sCC (ro + g m ro R1 + RZ )](1 + sC1RZ ) RX QωS ωS

• 1st zero of error amp placed near output filter pole • ESR zero and 2nd pole of error amp are placed out of loop bandwidth BW obtained by setting | LG |= 1 : | LG ( sBW ) |≈ BW =

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1 RSEN

⋅

RZ =1 sBW C R1 1

⋅

1 RZ 1 2π R1 RSEN C 23


Voltage Mode Boost

VIN

L

S2

VSW

VOUT CLK R1

RESR D’ D

S1

VRAMP RL

VEA R2

C

VSW VIN

IL D

Q

S

QB R

11/1/2007

IOUT

CLK RST

VRAMP VEA

VFB EA


VREF

24

Voltage Mode Boost Voltage Mode Boost Transfer Functions: vO VIN ≈ d (1 − D) 2 s 2 (1 − D) , ω0 = LC

(1 + sCRESR )(1 − s

L ) 2 RL (1 − D)

LC L s ( + + CRESR ) + 1 (1 − D) 2 RL (1 − D) 2

ωRHP

RL (1 − D) 2 , = L

Q=

=

VIN (1 − D) 2

(1 +

s

ωZ

)(1 −

s

ωRHP

)

s s2 1+ + Qω0 ω0 2

1 1 (1 − D) RL

L C + (1 − D) RESR C L

and d 1 = a(s) vFB VR where a ( s ) is the transfer function of the error amplifier

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25

Voltage Mode Boost - Effective Inductance Perturbation from Output to Inductor Current: diL (1 − D)vo = VIN − (1 − D)VO ⇒ iL = dt sL and L

I O = I L (1 − D) ⇒ io = iL (1 − D)

Impedance looking into the Inductor from Output: ZO =

vo sL = io (1 − D) 2

Thus the Effective Inductance

Leff =

L (1 − D) 2

This makes the ω0 of the LC Filter to Move with D 11/1/2007


26

Voltage Mode Boost - RHP Zero Perturbation from Duty Cycle to Output Current: I O = I L (1 − D ) ⇒ io = iL (1 − D ) − d ⋅ I L = iL (1 − D ) − d ⋅ L

IO 1− D

d ⋅ VO diL = DVIN + (1 − D)(VIN − VO ) ⇒ iL ≈ dt sL

Right-Half-Plan Zero forms at frequency where: |

I d ⋅ VO (1 − D) |=| d ⋅ O | 1− D jω RHP L

ω RHP

RL (1 − D) 2 = L

Right-Half-Plan Zero exists for both Voltage Mode and Current Mode Boost 11/1/2007


27

Voltage Mode Boost Control (Duty Cycle) to Output Transfer Function: Example: L=2.2uH, C=10uF, RESR=10m Ohm, VIN=2.5V, VOUT=5V, 10V, 15V, IOUT=100mA FSW=1.5MHz ω0 and ωRHP moves lower with increased duty cycle

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28

Voltage Mode Boost – Type-III Error Amp Usually Type-III Compensation Network is Required: C3

C2

R2 VFB R3

C1

R1

EA

VEA

VREF

vEA (1 + sC1R1 )[1 + s ( R3 + R2 )C2 ] ≈ − A0 vFB [1 + sR3 (1 + A0 )(C1 + C3 )](1 + sR2C2 )(1 + sR1C3 || C1 ) LG ≈ − A0

(1 + sC1R1 )(1 + sR3C2 ) VIN ⋅ [1 + sR3 A0C1 ](1 + sR2C2 )(1 + sR1C3 ) VR (1 − D ) 2

Set BW to be lower than ωZ and ω RHP : BW : R1 ⋅ C2 ⋅

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VIN 1 1 = 1 ⇒ BW = VR sBW LC 2π

R1 ⋅ C2 ⋅ LC

VIN VR

(1 +

s

ωZ

1+

)(1 −

s

ω RHP

s s2 + 2 Qω0 ω0

)

Example Design Steps: 1. Estimate worst case ωRHP=300kHz 2. Set BW<100k: R1C2<2.75µs 3. Set both zeros near ω0: R1=100k, C1=100pF, R3=300k, C2=20pF, ωz1=16.0kHz, ωz2=26.5kHz 4. Bandwidth: fBW= 80kHz 5. Mid-band DC gain of 1/3 6. Set 2nd and 3rd pole to beyond ωRHP : R2=10k, C3=3pF ωp2=530kHz, ωp3=790kHz


29

Voltage Mode Boost – Type-III Error Amp

• Adjust C1 to move 1st zero • Adjust R3 to move 2nd zero and mid-band gain • 2nd pole and 3rd poles suppress high frequency noise 11/1/2007

• Phase shift exceeds 180° at ω0 -> conditionally stable • Move 1st zero lower to improve phase shift -> much larger C1


30


VIN

Current Mode Boost L

VSW

S2

VOUT CLK

R1

RESR D’

RL

VRAMP

S1

D

VEA

R2

C

RST VSW

VIN

RSEN Slope Comp D

Q

S

QB R

IL

CLK RST

VRAMP VEA

VFB

IOUT

EA VREF

11/1/2007


31

Current Mode Boost Transfer Function of the Current Loop: Gm = RX VIN

Gm

IO

VOUT R1

RESR RL

R2

C

io 1 − D 1 = vEA RSEN 1 + RL 2 RX

where RX =

Similar to Peak Current Mode Buck Delay and sampling effect results in a 2 - pole system : Gm ( s ) ≈

VEA

VFB EA VREF

L 1 2L ( || ) 2 (1 − D) T [(1 + ma )(1 − D) − 0.5] DTS S m1

ωS = Q=

1− D 1 1 s s2 RSEN 1 + RL 1+ + 2 RX QωS ωS 2

π TS 2

1

π (1 + ma )(1 − D) − 0.5 m1

11/1/2007


=

2

1

π 1 − 2 D(1 − ma ) m2

32

Current Mode Boost Control to Output Transfer Function: vo (1 − D) RL 1 1 = Gm ( s) ⋅ Z O = ⋅ vEA 2 RSEN 1 + RL 1 + s + ( s ) 2 ωS QωS 2 RX

ωRHP

(1 + sCRESR )(1 − [1 + sC (

s

ωZRHP

)

RL || RX )] 2

RL (1 − D) 2 = L

Example: VIN=2.5V VOUT= 5V, 10V, 15V, 20V L=2.2uH, C=10uF RESR=10m Ohm IOUT = 100mA RSEN = 0.5 Ohm FSW = 1.5MHz

11/1/2007


33

Current Mode Boost – Error Amp Ex. Use the same error amp structure as on page 22: The Complete Loop Transfer Function: (1 − D) RL 1 1 T (s) = − ⋅ 2 RSEN 1 + RL 1 + s + ( s ) 2 2 RX QωS ωS

(1 + sCRESR )(1 − s [1 + sC (

s

ωZRHP

RL || RX )] 2

C1

CC

RZ

R1 VFB EA

VEA

VREF

) ⋅ A0

1 + sCC RZ [1 + sCC (ro + g m ro R1 + RZ )](1 + sC1RZ )

Generally Guideline: • To ensure loop stability, the unity-gain bandwidth is set to be 3-5x lower than the worst case RHP zero • The ESR zero and 2nd pole of the amplifier is placed higher than the RHP zero • The current loop poles are usually much higher than RHP zero 11/1/2007


34

Current Mode Boost – Error Amp Ex. Loop Bandwidth can be estimated as: BW =

1 (1 − D) RZ ωRHP ⋅ ≤ 2π RSEN C R1 3

Since ωRHP

(RHP zero contributes < 18o phase shift) 2

V V ∝ RL (1 − D) = RL ( IN ) 2 = IN , BW ∝ (1 − D) VO VO ⋅ I O 2

Bandwidth should be set at max. duty cycle and load Example: VIN=2.5V, VOUT=5V, IO=500mA L=2.2uH, C=10uF, RSEN=0.5 Ohm, RZ=1M Ohm, ωZRHP=181kHz, BW chosen to be ~60kHz Calculate: R1:~300k Ohm 11/1/2007


35

Current Mode Boost Complete Loop Transfer Function of Current Mode Boost Converter: Error Amplifier Example: R1=250k, RZ=1M CC=25pF, C1=0.3pF Output Current: 1mA, 10mA, 100mA, 500mA Loop BW: ~60kHz

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36

DC-DC Converter – Building Blocks

PWM Comparator

Multi-Stage Gain -> Faster For Small Input Signal But, High-Gain Stage Has Longer Recovery Time So, Usually Low-Gain Amp(s) Followed by High-Gain Comparator

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37

Building Blocks – PWM Comparator OTA based comparator with pre-amps

INP

INN COMP

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OUT

38

Building Blocks – Error Amplifiers

Error Amplifiers

Folded-Cascode Error Amplifier

OUT

INN

Good: • Input Common Mode Down to Ground • Smaller Input Offset than OTA

INP BIAS

11/1/2007

But: • Difficult to get large Gm


39

Building Blocks – Error Amplifiers

Constant Gm Error Amplifier

I1

I1 R OUT

INN

INP

I2

11/1/2007

I2

Good: • Constant Gm Defined by R • Scalable Gm by Current Mirrors But: • Higher Input Offset due to Even More Current Mirrors • Additional Gm Regulation Loop


40

DC-DC Converter Design Acknowledgement: Jian Zhou etc. for Review and Suggestions

Thank You For Your Attendance

11/1/2007


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Design of DC-DC Converters - IEEE Entity Web Hosting

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