EECE488: Analog CMOS Integrated Circuit Design

EECE488: Analog CMOS Integrated Circuit Design Introduction and Background Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British Columbia [email protected] Technical contributions of Pedram Lajevardi in revising the slides is greatly acknowledged. SM

EECE 488 – Set 1: Introduction and Background

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Marking

Assignments

10% (4 to 6)

Midterm

15%

Project

25%

Final Exam

50%

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References • •

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Main reference: Lecture notes Recommended Textbook: Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill, 2001 Some other useful references: T. Chan Carusone, D. Johns and K. Martin, Analog Integrated Circuit Design, 2nd Edition, John Wiley, 2011 P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits, 5th Edition, John Wiley, 2009 D. Holberg and P. Allen, CMOS Analog Circuit Design, 3rd Edition, Oxford University Press, 2011 R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, Wiley-IEEE Press, 2010 A. Sedra and K.C. Smith, Microelectronic Circuits, 5th or 6th Edition, Oxford University Press, 2004, 2009 Journal and conference articles including IEEE Journal of Solid-State Circuits and International Solid-State Circuits Conference EECE 488 – Set 1: Introduction and Background

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Fun to Check William F. Brinkman, Douglas E. Haggan, and William W. Troutman, “A History of the Invention of the Transistor and Where It Will Lead Us,” IEEE Journal of Solid-State Circuits, volume 32, no. 12, December 1997, pp. 1858-1865 http://download.intel.com/newsroom/kits/22nm/pdfs/Intel_Transistor_Backgrounder.pdf

Boris Murmann, “Digitally Assisted Analog Circuits,” IEEE Micro, vol. 26, no. 2, pp. 38-47, Mar. 2006. Interesting CAD Tools by Dr. Michael Perrott and his group: http://www.cppsim.com/download_hspice_tools.html

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Why Analog? •

Most of the physical signals are analog in nature!

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Although digital is great we need an analog interface to convert physical signals from analog to digital

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Also, in some application after processing the signals in digital domain, we need to convert them back to analog.

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Thus in many applications analog and mixed-signal circuits are the performance bottlenecks.

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Also with constant process improvements the boundary of between high-speed digital and analog circuits becomes more and more fuzzy!

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That is why analog and mixed-signal designers are still and hopefully will be in demand for the foreseeable future.

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AFE

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DSP

Example:

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Data Converter

Typical Real World System

Filter

ADC


DSP

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Intel’s Tick-Tock Model

Tick (process technology advancement), Tock (new microarchitecture) http://www.intel.com/content/www/us/en/silicon-innovations/intel-tick-tock-model-general.html SM


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Intel 45 nm Process

http://blog.oregonlive.com/siliconforest/2007/11/intel11.pdf SM

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Background 1. Suggested Reading 2. Structure of MOS Transistors 3. Threshold Voltage 4. Long-Channel Current Equations 5. Regions of Operation 6. Transconductance 7. Second-Order Effects 8. Short-Channel Effects 9. MOS Layout 10. Device Capacitances 11. Small-signal Models 12. Circuit Impedance 13. Equivalent Transconductance SM


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Suggested Reading •

Most of the material in this set are based on

Chapters 2, 16, and 17 of the Razavi’s book: Design of Analog CMOS Integrated Circuits

Many of the figures in this set are from © Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001, unless otherwise noted.

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Transistor •

Transistor stands for …

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Transistor are semiconductor devices that can be classified as – Bipolar Junction Transistors (BJTs) – Field Effect Transistors (FETs) • Depletion-Mode FETs or (e.g., JFETs)

• Enhancement-Mode FETs (e.g., MOSFETs)

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Simplistic Model •

MOS transistors have three terminals: Gate, Source, and Drain

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The voltage of the Gate terminal determines the type of connection between Source and Drain (Short or Open). Thus, MOS devices behave like a switch

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NMOS

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PMOS

VG high

Device is ON D is shorted to S

Device is OFF D & S are disconnected

VG low

Device is OFF Device is ON D & S are disconnected D is shorted to S


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Physical Structure - 1 • •

Source and Drain terminals are identical except that Source provides charge carriers, and Drain receives them. MOS devices have in fact 4 terminals: – Source, Drain, Gate, Substrate (bulk)

© Microelectronic Circuits, 2004 Oxford University Press SM

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Physical Structure - 2 • • • •

Charge Carriers are electrons in NMOS devices, and holes in PMOS devices. Electrons have a higher mobility than holes So, NMOS devices are faster than PMOS devices We rather to have a p-type substrate?! LD: Due to Side Diffusion Poly-silicon used instead of Metal for fabrication reasons

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Actual length of the channel (Leff) is less than the length of gate EECE 488 – Set 1: Introduction and Background

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Physical Structure - 3 •

N-wells allow both NMOS and PMOS devices to reside on the same piece of die.

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As mentioned, NMOS and PMOS devices have 4 terminals: Source, Drain, Gate, Substrate (bulk) In order to have all PN junctions reverse-biased, substrate of NMOS is connected to the most negative voltage, and substrate of PMOS is connected to the most positive voltage.

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Physical Structure - 4 •

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electron In NMOS Devices: Source → Drain Current flows from Drain to Source

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In PMOS Devices: Source hole → Drain Current flows from Source to Drain

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Current flow determines which terminal is Source and which one is Drain. Equivalently, source and drain can be determined based on their relative voltages.

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MOS transistor Symbols:


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Threshold Voltage - 1 •

Consider an NMOS: as the gate voltage is increased, the surface under the gate is depleted. If the gate voltage increases more, free electrons appear under the gate and a conductive channel is formed.

(a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion, and (d) channel formation

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As mentioned before, in NMOS devices charge carriers in the channel under the gate are electrons. EECE 488 – Set 1: Introduction and Background

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Intuitively, the threshold voltage is the gate voltage that forces the interface (surface under the gate) to be completely depleted of charge (in NMOS the interface is as much n-type as the substrate is p-type)

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Increasing gate voltage above this threshold (denoted by VTH or Vt) induces an inversion layer (conductive channel) under the gate.

© Microelectronic Circuits, 2004 Oxford University Press SM

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Threshold Voltage - 3 Analytically:

VTH = Φ MS + 2 ⋅ Φ F +

Qdep C ox

Where:

Φ MS = Built - in Potential = Φ gate − Φ Silicon = the difference between the work functions of the polysilicon gate and the silicon substrate Φ = Work Function (electrost atic potential) = F

N K ⋅T ⋅ ln q  n

sub

i

Q = Charge in the depletion region = dep

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4⋅ q ⋅ε ⋅ Φ ⋅ N


si

F

  

sub

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In practice, the “native” threshold value may not be suited for circuit design, e.g., VTH may be zero and the device may be on for any positive gate voltage.

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Typically threshold voltage is adjusted by ion implantation into the channel surface (doping P-type material will increase VTH of NMOS devices).

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When VDS is zero, there is no horizontal electric field present in the channel, and therefore no current between the source to the drain.

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When VDS is more than zero, there is some horizontal electric field which causes a flow of electrons from source to drain.

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Long Channel Current Equations - 1 •

The voltage of the surface under the gate, V(x), depends on the voltages of Source and Drain.

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If VDS is zero, VD= VS=V(x). The charge density Qd (unit C/m) is uniform. Qd =

− Q − C ⋅ V − (C oxWL ) ⋅ (VGS − VTH ) = = L L L

Qd = −WC ox (VGS − VTH ) •

If VDS is not zero, the channel is tapered, and V(x) is not constant. The charge density depends on x.

Qd ( x) = −WC ox (VGS − V ( x) − VTH )

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Current :

dQ dQ dx = × = Qd ⋅ velocity dt dx dt Velocity in terms of V(x): dV velocity = µ ⋅ E , E = − dt − dV ( x) → velocity = ( µ ⋅ ) I=

dx

Qd in terms of V(x): Qd ( x) = −WC ox (VGS − V ( x) − VTH )

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Current in terms of V(x): I D = WC ox [VGS − V ( x) − VTH ]µ n L

VDS

x =0

V =0

dV ( x ) dx

© Microelectronic Circuits, 2004 Oxford University Press

∫ I D dx = ∫ WC ox µ n [VGS − V ( x) − VTH ]dV

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Long-channel current equation: I D = µ n C ox SM

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W 1 2 [(VGS − VTH )V DS − V DS ] L 2 EECE 488 – Set 1: Introduction and Background

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If VDS ≤ VGS-VTH we say the device is operating in triode (or linear) region.

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Current in Triode Region:

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Terminology:

I D = µ n ⋅ C ox ⋅

W L

1 2   ⋅ (VGS − VTH ) ⋅ VDS − ⋅ V DS  2 

W L Overdrive Voltage = Effective Voltage = VGS − VTH = Veff Aspect Ratio =

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For very small VDS (deep Triode Region): ID can be approximated to be a linear function of VDS. The device resistance will be independent of VDS and will only depend on Veff. The device will behave like a variable resistor

If VDS << 2(VGS − VTH ) : W ⋅ (VGS − VTH ) ⋅ VDS L 1 = W µ n ⋅ C ox ⋅ ⋅ (VGS − VTH ) L

I D = µ n ⋅ C ox ⋅ RON =

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VDS ID


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Increasing VDS causes the channel to acquire a tapered shape. Eventually, as VDS reaches VGS – VTH the channel is pinched off at the drain. Increasing VDS above VGS – VTH has little effect (ideally, no effect) on the channel’s shape.


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When VDS is more than VGS – VTH the channel is pinched off, and the horizontal electric field produces a current. SM


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If VDS > VGS – VTH, the transistor is in saturation (active) region, and the channel is pinched off.

L'

VGS −VTH

x=0

V =0

∫ I D dx =

ID =

1 W µ n C ox (VGS − VTH ) 2 2 L'

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Let’s, for now, assume that L’=L. The fact that L’ is not equal to L is a second-order effect known as channel-length modulation.

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Since ID only depends on VGS, MOS transistors in saturation can be used as current sources.

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∫ WC ox µ n [VGS − V ( x) − VTH ]dV


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Current Equation for NMOS:  0 ; if VGS < VTH (Cut − off )    W µ n ⋅ C ox ⋅ ⋅ (VGS − VTH ) ⋅ VDS ; if VGS > VTH , VDS << 2(VGS − VTH ) ( Deep Triode) L  =  W 1 2 µ n ⋅ C ox ⋅ ⋅ (VGS − VTH ) ⋅ V DS − ⋅ VDS ; if VGS > VTH , VDS < VGS − VTH (Triode) L 2     1 ⋅ µ ⋅ C ⋅ W ⋅ (V − V ) 2 ; if V > V , V > V − V ( Saturation ) n ox GS TH GS TH DS GS TH  2 L

I D = I DS

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Current Equation for PMOS:

I D = I SD

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 0 ; if VSG < VTH (Cut − off )    W µ p ⋅ C ox ⋅ ⋅ (VSG − VTH ) ⋅ V SD ; if VSG > VTH , VSD << 2(VSG − VTH ) ( Deep Triode) L  =  W 1 2 µ p ⋅ C ox ⋅ ⋅ (VSG − VTH ) ⋅ V SD − ⋅ VSD ; if VSG > VTH , VSD < VSG − VTH (Triode) L 2     1 ⋅ µ ⋅ C ⋅ W ⋅ (V − V ) 2 ; if V > V , V > V − V ( Saturation ) SG TH SG TH SD SG TH  2 p ox L

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Regions of Operation - 1 •

Regions of Operation: Cut-off, triode (linear), and saturation (active or pinch-off)


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Once the channel is pinched off, the current through the channel is almost constant. As a result, the I-V curves have a very small slope in the pinch-off (saturation) region, indicating the large channel resistance. EECE 488 – Set 1: Introduction and Background

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The following illustrates the transition from pinch-off to triode region for NMOS and PMOS devices.

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For NMOS devices: If VD increases (VG Const.), the device will go from Triode to Pinch-off. If VG increases (VD Const.), the device will go from Pinch-off to Triode. ** In NMOS, as VDG increases the device will go from Triode to Pinch-off. • For PMOS devices: If VD decreases (VG Const.), the device will go from Triode to Pinch-off. If VG decreases (VD Const.), the device will go from Pinch-off to Triode. ** In PMOS, as VGD increases the device will go from Pinch-off to Triode. SM

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NMOS Regions of Operation:


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Relative levels of the terminal voltages of the enhancement-type NMOS transistor for different regions of operation.


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PMOS Regions of Operation:


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The relative levels of the terminal voltages of the enhancement-type PMOS transistor for different regions of operation.


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Regions of Operation - 5 Example: For the following circuit assume that VTH=0.7V. • When is the device on?

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What is the region of operation if the device is on?

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Sketch the on-resistance of transistor M1 as a function of VG.

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Transconductance - 1 •

The drain current of the MOSFET in saturation region is ideally a function of gate-overdrive voltage (effective voltage). In reality, it is also a function of VDS.

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It makes sense to define a figure of merit that indicates how well the device converts the voltage to current.

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Which current are we talking about?

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What voltage is in the designer’s control?

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What is this figure of merit? gm =

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∂I D ∂VGS VDS = Const.


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Transconductance - 2 Example: Plot the transconductance of the following circuit as a function of VDS (assume Vb is a constant voltage).

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Transconductance in triode:

[

]

∂  W 1 2   µ n ⋅ C ox ⋅ ⋅ (VGS − VTH ) ⋅ VDS − ⋅ VDS  ∂VGS  L 2  V DS = Const. W = µ n ⋅ C ox ⋅ ⋅ VDS L

gm =

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Transconductance in saturation: ∂ 1 W 2   ⋅ µ n ⋅ C ox ⋅ ⋅ (VGS − VTH )  ∂VGS  2 L  VDS = Const . W = µ n ⋅ C ox ⋅ ⋅ (VGS − VTH ) L

gm =

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Moral: Transconductance drops if the device enters the triode region.

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Transconductance - 3 •

Transconductance, gm, in saturation:

g m = µ n ⋅ C ox ⋅ •

If the aspect ratio is constant: gm depends linearly on (VGS - VTH). Also, gm depends on square root of ID.

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If ID is constant: gm is inversely proportional to (VGS - VTH). Also, gm depends on square root of the aspect ratio.

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If the overdrive voltage is constant: gm depends linearly on ID. Also, gm depends linearly on the aspect ratio.

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2⋅ ID W W ⋅ (VGS − VTH ) = 2 µ n ⋅ C ox ⋅ ⋅ I D = L L VGS − VTH


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Second-Order Effects (Body Effect) Substrate Voltage: • So far, we assumed that the bulk and source of the transistor are at the same voltage (VB=VS). • If VB >Vs, then the bulk-source PN junction will be forward biased, and the device will not operate properly. • If VB
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It can be shown that (what is the unit for γ ?):

VTH = VTH 0 + γ ⋅  2 ⋅ Φ F + VSB −  SM

2 ⋅ Φ F  where γ = 

2 ⋅ q ⋅ ε si ⋅ N sub Cox


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Body Effect - 2 Example: Consider the circuit below (assume the transistor is in the active region): • If body-effect is ignored, VTH will be constant, and I1 will only depend on VGS1=Vin-Vout. Since I1 is constant, Vin-Vout remains constant.

Vin − Vout − VTH = C = Const. → Vin − Vout = VTH + C = D = Conts. •

In general, I1 depends on VGS1- VTH =Vin-Vout-VTH (and with body effect VTH is not constant). Since I1 is constant, Vin-Vout-VTH remains constant:

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As Vout increases, VSB1 increases, and as a result VTH increases. Therefore, Vin-Vout Increases.

Vin − Vout − VTH = C = Const. → Vin − Vout = VTH + C

No Body Effect SM

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With Body Effect


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Body Effect - 3 Example: For the following Circuit sketch the drain current of transistor M1 when VX varies from -∞ to 0. Assume VTH0=0.6V, γ=0.4V1/2, and 2ΦF=0.7V.

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Channel Length Modulation - 1 •

When a transistor is in the saturation region (VDS > VGS – VTH), the channel is pinched off.

L

•

1 1 1 1 = = ⋅ L ' L − ∆L L 1 − ∆L ∆L

(

L

(

)

1 1 1 ≈ ⋅ 1 + ∆L = ⋅ (1 + λ ⋅ VDS ) L L L' L

Assuming

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The drain current is I D = µ n C ox

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As ID actually depends on both VGS and VDS, MOS transistors are not ideal current sources (why?).

L

= λ ⋅ V DS

we get:

)

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1 W (VGS − VTH ) 2 where L' = L-∆L 2 L' 1 ≈ ⋅ 1 + ∆L L L

The drain current is I D = µnCox

1 2

W 1 W 2 (VGS − VTH ) 2 ≈ µ n C ox (VGS − VTH ) ⋅ (1 + λ ⋅ VDS ) L' 2 L


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Channel Length Modulation - 2 •

λ represents the relative variation in effective length of the channel for a given increment in VDS.

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For longer channels λ is smaller, i.e., λ ∝ 1/L

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Transconductance: In Triode:

gm =

g m = µ n ⋅ C ox ⋅

∂I D ∂VGS V DS = Const.

W ⋅ VDS L

In Saturation (ignoring channel length modulation): g m = µ n ⋅ Cox ⋅

2⋅ ID W W ⋅ (VGS − VTH ) = 2µ n ⋅ Cox ⋅ ⋅ I D = L L VGS − VTH

In saturation with channel length modulation: g m = µ n ⋅ Cox ⋅

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2⋅ ID W W ⋅ (VGS − VTH ) ⋅ (1 + λ ⋅ VDS ) = 2 µ n ⋅ C ox ⋅ ⋅ I D ⋅ (1 + λ ⋅ VDS ) = L L VGS − VTH

The dependence of ID on VDS is much weaker than its dependence on VGS.

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Channel Length Modulation - 3 Example: Given all other parameters constant, plot ID-VDS characteristic of an NMOS for L=L1 and L=2L1

[(

W ⋅ VGS − VTH L ∂I D W Therefore : ∝ ∂VDS L I D ≈ µ n ⋅ Cox ⋅

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In Triode Region:

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In Saturation Region:

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DS −

1 2 ⋅ VDS 2

]

1 W µnCox (VGS − VTH )2 ⋅ (1 + λ ⋅ VDS ) 2 L 1 W ∂I D So we get : = µ nCox (VGS − VTH )2 ⋅ λ ∂VDS 2 L ID ≈

Therefore :

•

)⋅ V

W ⋅λ W ∂I D ∝ ∝ L ∂VDS L2

Changing the length of the device from L1 to 2L1 will flatten the ID-VDS curves (slope will be divided by two in triode and by four in saturation). Increasing L will make a transistor a better current source, while degrading its current capability. Increasing W will improve the current capability. EECE 488 – Set 1: Introduction and Background

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Sub-threshold Conduction • • •

If VGS < VTH, the drain current is not zero. The MOS transistors behave similar to BJTs. In BJT: I C = I S ⋅ e

VBE VT

VGS

ζ ⋅VT

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In MOS: I D = I 0 ⋅ e

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As shown in the figure, in MOS transistors, the drain current drops by one decade for approximately each 80mV of drop in VGS.

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In BJT devices the current drops faster (one decade for approximately each 60mv of drop in VGS).

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This current is known as sub-threshold or weak-inversion conduction.

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CMOS Processing Technology •

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Top and side views of a typical CMOS process


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CMOS Processing Technology •

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Different layers comprising CMOS transistors


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Photolithography (Lithography) •

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Used to transfer circuit layout information to the wafer


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Typical Fabrication Sequence

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Self-Aligned Process •

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Why source and drain junctions are formed after the gate oxide and polysilicon layers are deposited?


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Back-End Processing •

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Oxide spacers and silicide


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Contact and metal layers fabrication


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Large contact areas should be avoided to minimize the possibility of spiking


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MOS Layout - 1 •

It is beneficial to have some insight into the layout of the MOS devices.

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When laying out a design, there are many important parameters we need to pay attention to such as: drain and source areas, interconnects, and their connections to the silicon through contact windows. Design rules determine the criteria that a circuit layout must meet for a given technology. Things like, minimum length of transistors, minimum area of contact windows, …

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MOS Layout - 2 Example: Figures below show a circuit with a suggested layout.

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The same circuit can be laid out in different ways, producing different electrical parameters (such as different terminal capacitances).


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Device Capacitances - 1 • • • •

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The quadratic model determines the DC behavior of a MOS transistor. The capacitances associated with the devices are important when studying the AC behavior of a device. There is a capacitance between any two terminals of a MOS transistor. So there are 6 Capacitances in total. The Capacitance between Drain and Source is negligible (CDS=0).

These capacitances will depend on the region of operation (Bias values).


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Device Capacitances - 2 •

The following will be used to calculate the capacitances between terminals: ε C = W ⋅ L⋅C , C = 1. Oxide Capacitance: t ox

1

ox

ox

ox

q ⋅ ε si ⋅ N sub 4⋅ΦF

2.

Depletion Capacitance:

C 2 = C dep = W ⋅ L ⋅

3.

Overlap Capacitance:

C 3 = C 4 = C ov = W ⋅ LD ⋅ C ox + C fringe

4.

Junction Capacitance: Sidewall Capacitance:

C jsw

Bottom-plate Capacitance:

C jun = Cj

C j0  VR  1 +   ΦB 

m

C 5 = C 6 = C j + C jsw

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Device Capacitances - 3 In Cut-off: 1. CGS: is equal to the overlap capacitance. C = C = C 2. CGD: is equal to the overlap capacitance. C = C = C 3. CGB: is equal to Cgate-channel = C1 in series with Cchannel-bulk = C2. 4. 5.

GS

ov

3

GD

ov

4

CSB: is equal to the junction capacitance between source and bulk. CDB: is equal to the junction capacitance between source and bulk. C SB = C 5 C DB = C 6

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Device Capacitances - 4 In Triode: • The channel isolates the gate from the substrate. This means that if VG changes, the charge of the inversion layer are supplied by the drain and source as long as VDS is close to zero. So, C1 is divided between gate and drain terminals, and gate and source terminals, and C2 is divided between bulk and drain terminals, and bulk and source terminals. C 1. CGS: CGS = C ov + 21 2. CGD: C GD = Cov + C1 2 3. CGB: the channel isolates the gate from the substrate. CGB = 0 C2 C SB = C5 + 4. CSB: 2 C 5. CDB: C DB = C 6 + 2 2

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Device Capacitances - 5 In Saturation: • The channel isolates the gate from the substrate. The voltage across the channel varies which can be accounted for by adding two equivalent capacitances to the source. One is between source and gate, and is equal to two thirds of C1. The other is between source and bulk, and is equal to two thirds of C2. 2 C =C + C 1. CGS: 3 2. CGD: C =C 3. CGB: the channel isolates the gate from the substrate. C = 0 2 4. CSB: C =C + C 3 5. CDB: C =C GS

ov

GD

1

ov

GB

SB

DB

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5

2

6


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Device Capacitances - 6 •

In summary: Cut-off

Saturation

CGS

C ov

C ov +

C1 2

2 C ov + C1 3

CGD

C ov

C ov +

C1 2

C ov

CGB

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Triode

C1 ⋅ C 2 〈C GB 〈C1 C1 + C 2

0

0

2 C5 + C 2 3

CSB

C5

C C5 + 2 2

CDB

C6

C6 +

C2 2


C6

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Importance of Layout Example (Folded Structure): Calculate the gate resistance of the circuits shown below.

Folded structure: • Decreases the drain capacitance • Decreases the gate resistance • Keeps the aspect ratio the same SM

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Passive Devices •

Resistors

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Passive Devices •

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Capacitors:


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Passive Devices •

Capacitors

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Passive Devices •

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Inductors


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Latch-Up •

Due to parasitic bipolar transistors in a CMOS process

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Small Signal Models - 1 •

Small signal model is an approximation of the large-signal model around the operation point.

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In analog circuits most MOS transistors are biased in saturation region.

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In general, ID is a function of VGS, VDS, and VBS. We can use this Taylor series approximation: Taylor Expansion : I D = I D 0 + ∆I D ≈

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∂I D ∂I ∂I ⋅ ∆VGS + D ⋅ ∆VDS + D ⋅ ∆VBS + second order terms ∂VGS ∂V DS ∂V BS

∂I D ∂I ∂I ∆V DS ⋅ ∆VGS + D ⋅ ∆VDS + D ⋅ ∆VBS = g m ⋅ ∆VGS + + g mb ⋅ ∆V BS ∂VGS ∂VDS ∂VBS ro


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Small Signal Models - 2 1 2

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Current in Saturation: I D = µ n C ox

•

Taylor approximation: ∆I D ≈

•

Partial Derivatives:

W 1 W 2 (VGS − VTH ) 2 ≈ µ n C ox (VGS − VTH ) ⋅ (1 + λ ⋅ VDS ) L' 2 L

∂I D ∂I ∂I ⋅ ∆VGS + D ⋅ ∆V DS + D ⋅ ∆VBS ∂VGS ∂VDS ∂VBS

∂I D W = µ n ⋅ C ox ⋅ ⋅ (VGS − VTH ) ⋅ (1 + λ ⋅ V DS ) = g m ∂VGS L ∂I D 1 W 1 = ⋅ µ n ⋅ C ox ⋅ ⋅ (VGS − VTH ) 2 ⋅ λ ≈ I D ⋅ λ = ∂V DS 2 L ro ∂I D ∂I D ∂VTH  γ W   = ⋅ = − µ n ⋅ C ox ⋅ ⋅ (VGS − VTH ) ⋅ (1 + λ ⋅ V DS ) ⋅ − ∂V BS ∂VTH ∂V BS  L   2 2 ⋅ Φ F + VSB  γ = − g m ⋅ −  2 2 ⋅ Φ F + VSB  SM

   

  = g m ⋅η = g mb  


67


Small-Signal Model: i D = g m ⋅ vGS +

•

•

SM

SM

v DS + g mb ⋅ v BS ro

Terms, gmvGS and gmbvBS, can be modeled by dependent sources. These terms have the same polarity: increasing vG, has the same effect as increasing vB. The term, vDS/ro can be modeled using a resistor as shown below.


68

34


Complete Small-Signal Model with Capacitances:

•

Small signal model including all the capacitance makes the intuitive (qualitative) analysis of even a few-transistor circuit difficult!

•

Typically, CAD tools are used for accurate circuit analysis

•

For intuitive analysis we try to find a simplest model that can represent the role of each transistor with reasonable accuracy.

SM


69

Circuit Impedance - 1 •

It is often useful to determine the impedance of a circuit seen from a specific pair of terminals.

•

The following is the recipe to do so: 1. Connect a voltage source, VX, to the port. 2. Suppress all independent sources. 3. Measure or calculate IX. R = X

V I

X

X

SM

SM


70

35

Circuit Impedance - 2 Example: • Find the small-signal impedance of the following current sources. • We draw the small-signal model, which is the same for both circuits, and connect a voltage source as shown below:

i = X

v v + g ⋅v = r r X

X

m

GS

o

R = X

o

v =r i X

o

X

SM

71


Circuit Impedance - 3 Example: • Find the small-signal impedance of the following circuits. • We draw the small-signal model, which is the same for both circuits, and connect a voltage source as shown below:

i = X

v v − g ⋅v − g ⋅v = + g ⋅v + g ⋅v r r X

X

m

GS

mb

BS

m

o

R = X

X

mb

X

o

v 1 1 1 = =r 1 i g g +g +g r X

o

X

m

m

mb

mb

o

SM

SM


72

36

Circuit Impedance - 4 Example: • Find the small-signal impedance of the following circuit. This circuit is known as the diode-connected load, and is used frequently in analog circuits. •

We draw the small-signal model and connect the voltage source as shown below: 1  v v i = + g ⋅ v = + g ⋅ v = v ⋅  + g  r r r   X

X

X

m

GS

m

o

R = X

X

X

m

o

o

v 1 1 = =r 1 i g +g r X

o

X

m

m

o

•

If channel length modulation is ignored (ro=∞) we get: R =r X

o

1 1 1 =∞ = g g g m

m

m

SM


73

Circuit Impedance - 5 Example: • Find the small-signal impedance of the following circuit. This circuit is a diode-connected load with body effect.

i = X

v v − g ⋅v − g ⋅v = + g ⋅v + g ⋅v r r X

X

m

GS

mb

BS

m

o

X

mb

X

o

1 = v ⋅  + g + g r X

m

o

mb

  

1 1 1 1 v R = = =r =r 1 i g + g g g +g +g r X

X

o

o

X

m

m

mb

m

mb

mb

o

•

If channel length modulation is ignored (ro=∞) we get: R =r X

o

1 1 1 1 1 =∞ = = g +g g +g g +g g g m

SM

SM

mb

m

mb

m

mb

m

mb


74

37

Equivalent Transconductance - 1 •

Recall that the transconductance of a transistor was a a figure of merit that indicates how well the device converts a voltage to current. ∂I g = ∂V V = Const. D

m

GS

•

DS

It is sometimes useful to define the equivalent transconductance of a circuit as follows: ∂I G = ∂V V = Const. OUT

m

IN

•

The following is a small-signal block diagram of an arbitrary circuit with a Norton equivalent at the output port. We notice that: VOUT=Constant so vOUT=0 in the small signal model.

G = m

i v v OUT

IN

SM

OUT

OUT

=0


75

Equivalent Transconductance - 2 Example: • Find the equivalent transconductance of an NMOS transistor in saturation from its small-signal model.

i

OUT

= g ⋅v = g ⋅v m

GS

i G = =g v

m

IN

OUT

m

m

IN

SM

SM


76

38

Equivalent Transconductance - 3 Example: • Find the equivalent transconductance of the following circuit when the NMOS transistor in saturation.

v =v +v =v +i IN

i

GS

S

GS

OUT

⋅R

S

v = g ⋅ v + g ⋅ v − = g ⋅ (v − i r S

OUT

m

GS

mb

BS

m

IN

OUT

⋅ R ) + g ⋅ (− i S

mb

OUT

⋅ R )−

⋅R r

i

OUT

S

O

S

O

 R  ⋅ 1 + g ⋅ R + g ⋅ R +  = g ⋅ v r   i g g ⋅r = = G = R v r + r ⋅ ( g ⋅ R + g ⋅ R )+ R 1+ g ⋅ R + g ⋅ R + r i

S

OUT

m

S

mb

S

m

IN

O

OUT

m

m

O

m

S

IN

m

S

mb

O

O

m

S

mb

S

S

S

O

SM


77

Short-Channel Effects •

Threshold Reduction – Drain-induced barrier lowering (DIBL)

•

Mobility degradation

•

Velocity saturation

•

Hot carrier effects – Substrate current – Gate current

•

Output impedance variation

SM

SM


78

39

Threshold Voltage Variation in Short Channel Devices •

The Threshold of transistors fabricated on the same chip decreases as the channel length decreases.

•

Intuitively, the extent of depletion regions associated with drain and source in the channel area, reduces the immobile charge that must be imaged by the charge on the gate.

SM


79

Drain-Induced Barrier Lowering (DIBL) When the channel is short, the drain voltage increases the channel surface potential, lowering the barrier to flow charge from source (think of increased electric field) and therefore, decreasing the threshold.

SM

SM


80

40

Effects of Velocity Saturation •

Due to drop in mobility at high electric fields

•

(a) Premature drain current saturation and (b) reduction in gm

SM


81

Hot Carrier Effects •

Short channel devices may experience high lateral drain-source electric field

•

Some carriers that make it to drain have high velocity (called “hot” carriers)

•

“Hot” carriers may “hit” silicon atoms at high speed and cause impact ionization

•

The resulting electron and holes are absorbed by the drain and substrate causing extra drain-substrate current

•

Really “hot” carriers may be injected into gate oxide and flow out of gate causing gate current!

SM

SM


82

41

Output Impedance Variation Recall the definition of λ.

SM


83

Output Impedance Variation in Short-Channel Devices

SM

SM


84

42

EECE488: Analog CMOS Integrated Circuit Design

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