√Hz Low Noise Instrumentation Amplifier Data Sheet AD8429

1 nV/√Hz Low Noise Instrumentation Amplifier AD8429

Data Sheet

PIN CONNECTION DIAGRAM

Low noise 1 nV/√Hz input noise 45 nV/√Hz output noise High accuracy dc performance (AD8429BRZ) 90 dB CMRR minimum (G = 1) 50 μV maximum input offset voltage 0.02% maximum gain accuracy (G = 1) Excellent ac specifications 80 dB CMRR to 5 kHz (G = 1) 15 MHz bandwidth (G = 1) 1.2 MHz bandwidth (G = 100) 22 V/μs slew rate THD: −130 dBc (1 kHz, G = 1) Versatile ±4 V to ±18 V dual supply Gain set with a single resistor (G = 1 to 10,000) Temperature range for specified performance −40°C to +125°C

AD8429

–IN

1

8

+VS

RG

2

7

VOUT

RG

3

6

REF

+IN

4

5

–VS 09730-001

FEATURES

TOP VIEW (Not to Scale)

Figure 1.

APPLICATIONS Medical instrumentation Precision data acquisition Microphone preamplification Vibration analysis

GENERAL DESCRIPTION

The AD8429 reliably amplifies fast changing signals. Its current feedback architecture provides high bandwidth at high gain, for example, 1.2 MHz at G = 100. The design includes circuitry to improve settling time after large input voltage transients. The AD8429 was designed for excellent distortion performance, allowing use in demanding applications such as vibration analysis. Gain is set from 1 to 10,000 with a single resistor. A reference pin allows the user to offset the output voltage. This feature can Rev. A

The AD8429 performance is specified over the extended industrial temperature range of −40°C to +125°C. It is available in an 8-lead plastic SOIC package. 1000

100 G=1

10

G = 10 G = 100

1

0.1

G = 1k

1

10

100

1k

10k

100k

FREQUENCY (Hz)

09730-002

The AD8429 excels at measuring tiny signals. It delivers ultralow input noise performance of 1 nV/√Hz. The high CMRR of the AD8429 prevents unwanted signals from corrupting the acquisition. The CMRR increases as the gain increases, offering high rejection when it is most needed. The high performance pin configuration of the AD8429 allows it to reliably maintain high CMRR at frequencies well beyond those of typical instrumentation amplifiers.

be useful to shift the output level when interfacing to a single supply signal chain.

NOISE (nV/√Hz)

The AD8429 is an ultralow noise, instrumentation amplifier designed for measuring extremely small signals over a wide temperature range (−40°C to +125°C).

Figure 2. RTI Voltage Noise Spectral Density vs. Frequency

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AD8429

Data Sheet

TABLE OF CONTENTS Features .............................................................................................. 1

Architecture ................................................................................ 15

Applications ....................................................................................... 1

Gain Selection ............................................................................. 15

Pin Connection Diagram ................................................................ 1

Reference Terminal .................................................................... 15

General Description ......................................................................... 1

Input Voltage Range ................................................................... 16

Revision History ............................................................................... 2

Layout .......................................................................................... 16

Specifications..................................................................................... 3

Input Bias Current Return Path ............................................... 17

Absolute Maximum Ratings ............................................................ 6

Input Protection ......................................................................... 17

Thermal Resistance ...................................................................... 6

Radio Frequency Interference (RFI) ........................................ 17

ESD Caution .................................................................................. 6

Calculating the Noise of the Input Stage ................................. 18

Pin Configuration and Function Descriptions ............................. 7

Outline Dimensions ....................................................................... 19

Typical Performance Characteristics ............................................. 8

Ordering Guide .......................................................................... 19

Theory of Operation ...................................................................... 15

REVISION HISTORY 2/2017—Rev, 0 to Rev. A Changes to Figure 2 .......................................................................... 1 Change to Input Current Parameter, Table 1 ................................ 3 Changes to Figure 20 and Figure 21............................................. 10 Changes to Figure 24 through Figure 27 ..................................... 11 Changes to Figure 28 and Figure 30............................................. 12 Change to Large Differential Input Voltage at High Gain Section .............................................................................................. 17 Changes to Figure 53 ...................................................................... 18 4/2011—Revision 0: Initial Version

Rev. A | Page 2 of 20

Data Sheet

AD8429

SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted. Table 1. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR at 5 kHz G=1 G = 10 G = 100

Test Conditions/Comments

A Grade Typ Max

Min

B Grade Typ

Max

Unit

VCM = ±10 V 80 100 120 134

90 110 130 140

dB dB dB dB

76 90 90

80 90 90

dB dB dB

90

90

dB

VCM = ±10 V

G = 1000 VOLTAGE NOISE, RTI Spectral Density 1: 1 kHz

Min

VIN+, VIN− = 0 V

Input Voltage Noise, eni Output Voltage Noise, eno

1.0 45

Peak to Peak: 0.1 Hz to 10 Hz G=1

1.0 45

nV/√Hz nV/√Hz

2

2

µV p-p

100

100

nV p-p

Spectral Density: 1 kHz

1.5

1.5

pA/√Hz

Peak to Peak: 0.1 Hz to 10 Hz

100

100

pA p-p

G = 1000 CURRENT NOISE

VOLTAGE OFFSET 2 Input Offset, VOSI

150

Average TC

0.1

Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Average TC Input Offset Current Average TC

50

1

0.1

1000 3

10

3

µV

0.3

µV/°C

500

µV

10

µV/°C

VS = ±5 V to ±15 V 90 110 130 130

100 120 130 130

dB dB dB dB

VIN+, VIN− = 0 V 300 250

150

nA pA/°C

30

250

15

100 15

nA pA/°C

15 4 1.2 0.15

15 4 1.2 0.15

MHz MHz MHz MHz

DYNAMIC RESPONSE Small Signal Bandwidth: –3 dB G=1 G = 10 G = 100 G = 1000


AD8429

Data Sheet A Grade

Parameter Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Settling Time 0.001% G=1 G = 10

Test Conditions/Comments 10 V step

Min

G=1 G>1 Gain Nonlinearity G = 1 to 1000

Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error

Max

Unit

0.75 0.65 0.85

0.75 0.65 0.85

µs µs µs

5

5

µs

0.9 0.9

0.9 0.9

µs µs

1.2 7

1.2 7

µs µs

22

22

V/µs

−130 −116 −113 −111

−130 −116 −113 −111

dBc dBc dBc dBc

0.0005

0.0005

%

G = 1 + (6 kΩ/RG) 1

10000

1

10000

V/V

0.02 0.15

% %

VOUT = ±10 V 0.05 0.3 VOUT = −10 V to +10 V RL = 10 kΩ

2

Gain vs. Temperature G=1 G>1 INPUT Impedance (Pin to Ground) 4 Input Operating Voltage Range 5 OUTPUT Output Swing Over Temperature

Typ

f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p

G = 100 GAIN 3 Gain Range Gain Error

Min

First five harmonics, f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p

G=1 G = 10 G = 100 G = 1000 THD + N

B Grade Max

10 V step

G = 100 G = 1000 Slew Rate G = 1 to 100 THD

Typ

2

2 5 −100

2

1.5||3

ppm 5 −100

ppm/°C ppm/°C

VS = ±4 V to ±18 V

−VS + 2.8

+VS − 2.5

−VS + 2.8

+VS − 2.5

GΩ||pF V

RL = 2 kΩ

−VS + 1.8 −VS + 1.9

+Vs − 1.2 +Vs − 1.3

−VS + 1.8 −VS + 1.9

+Vs − 1.2 +Vs − 1.3

V V

RL = 10 kΩ

−VS + 1.7 −VS + 1.8

+Vs − 1.1 +Vs − 1.2

−VS + 1.7 −VS + 1.8

+Vs − 1.1 +Vs − 1.2

V V mA

VIN+, VIN− = 0 V

1.5||3

35

35

10 70

10 70

−VS

kΩ µA V

+VS 1 0.01


0.05

1 0.01

0.05

V/V %

Data Sheet

AD8429 A Grade

Parameter POWER SUPPLY Operating Range Quiescent Current

Test Conditions/Comments

Min

Max

Min

±18 7 9

±4

6.7

+125

−40

±4 T = 125°C

TEMPERATURE RANGE For Specified Performance

B Grade

Typ

−40

Typ

Max

Unit

6.7

±18 7 9

V mA mA

+125

°C

Total voltage noise = √(eni2 + (eno/G)2 + eRG2). See the Theory of Operation section for more information. Total RTI VOS = (VOSI) + (VOSO/G). 3 These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table. 4 Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 5 Input voltage range of the AD8429 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more details. 1 2


AD8429

Data Sheet

ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE

Table 2. Parameter Supply Voltage Output Short-Circuit Current Duration Maximum Voltage at –IN, +IN1 Differential Input Voltage1 Gain ≤ 4 4 > Gain > 50 Gain ≥ 50 Maximum Voltage at REF Storage Temperature Range Specified Temperature Range Maximum Junction Temperature ESD Human Body Model Charge Device Model Machine Model 1

Rating ±18 V Indefinite ±VS

θJA is specified for a device in free air using a 4-layer JEDEC printed circuit board (PCB). Table 3. Package 8-Lead SOIC

±VS ±50 V/gain ±1 V ±VS −65°C to +150°C −40°C to +125°C 140°C

ESD CAUTION

3.0 kV 1.5 kV 0.2 kV

For voltages beyond these limits, use input protection resistors. See the Theory of Operation section for more information.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.


θJA 121

Unit °C/W

Data Sheet

AD8429

AD8429

–IN

1

8

+VS

RG

2

7

VOUT

RG

3

6

REF

+IN

4

5

–VS


09730-003

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions Pin No. 1 2, 3 4 5 6 7 8

Mnemonic −IN RG +IN −VS REF VOUT +VS

Description Negative Input Terminal. Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (6 kΩ/RG). Positive Input Terminal. Negative Power Supply Terminal. Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level shift the output. Output Terminal. Positive Power Supply Terminal.


AD8429

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, VS = ±15, VREF = 0, RL = 10 kΩ, unless otherwise noted. 15

160

VS = ±15V

G=1 10

120

VS = ±12V

POSITIVE PSRR (dB)

COMMON-MODE VOLTAGE (V)

GAIN = 1000 GAIN = 100 GAIN = 10 GAIN = 1

140

5

VS = ±5V

0

–5

100 80 60 40

–10

–10

–5

0

5

10

15

OUTPUT VOLTAGE (V)

0

09730-010

–15 –15

1

10

100

1k

10k

160

15

GAIN = 1000 GAIN = 100 GAIN = 10 GAIN = 1

VS = ±15V 140 120

VS = ±12V

NEGATIVE PSRR (dB)


10

5

VS = ±5V

0

1M

Figure 7. Positive PSRR vs. Frequency

Figure 4. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, VS = ±5 V, ±12 V, ±15 V (G = 1) G = 100

100k

FREQUENCY (Hz)

09730-069

20

–5

100 80 60 40

–10

–5

0

5

10

15

OUTPUT VOLTAGE (V)

0

10

1

60

–10

50 40

–12.28V

GAIN (dB)

–20 –25 +12.60V

20

–40

–10

–45

–20

–4

–2

0

2

4

6

8

10

12


14

1M

VS = ±15V

GAIN = 1000

GAIN = 100

GAIN = 10

10 0

–6

100k

30

–35

GAIN = 1

–30 100

09730-068

INPUT BIAS CURRENT (nA)

70

–5

–50 –14 –12 –10 –8

10k

Figure 8. Negative PSRR vs. Frequency

0

–30

1k

FREQUENCY (Hz)

Figure 5. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, VS = ±5 V, ±12 V, ±15 V (G = 100)

–15

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 6. Input Bias Current vs. Common-Mode Voltage

Figure 9. Gain vs. Frequency


10M

100M

09730-017

–10

09730-011

–15 –15

09730-070

20

AD8429 40

IB+ IB– IOS

G = 1k 140

G = 100 INPUT BIAS CURRENT (nA)

CMRR (dB)

30

G = 10

120

G=1

100

BANDWIDTH LIMITED

80 60 40 20

10

1

100

1k

10k

100k

1M

FREQUENCY (Hz)

10

1.5

0

1.0

–10

0.5

0

15

30

45

60

75

90

0 105 120 135

TEMPERATURE (°C)

40

120

30

G = 10

100

GAIN = 1

G = 100

G = 1k

20 10

G=1

80

CMRR (µV/V)

CMRR (dB)

2.0

Figure 13. Input Bias Current and Input Offset Current vs. Temperature

Figure 10. CMRR vs. Frequency 140

2.5

20

–20 –45 –30 –15

09730-110

0

3.0

09730-019

160

INPUT OFFSET CURRENT (nA)

Data Sheet

BANDWIDTH LIMITED

60

0 –10 –20 –30

40

–40

1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

Figure 14. CMRR vs. Temperature (G = 1), Normalized at 25°C

Figure 11. CMRR vs. Frequency, 1 kΩ Source Imbalance 12

10.0 9.5

10 SUPPLY CURRENT (mA)

9.0

8

6

4

8.5 8.0 7.5 7.0 6.5 6.0

2

0

0

100

200

300

400

500

600

700

WARM-UP TIME (s)

5.0 –50

–30

–10

10

30

50

70

90

110

TEMPERATURE (°C)

Figure 15. Supply Current vs. Temperature (G = 1)

Figure 12. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time


130

09730-022

5.5 09730-112

CHANGE IN INPUT OFFSET VOLTAGE (µV)

NORMALIZED AT 25°C

–60 –40

09730-111

0

–50

09730-114

20

Data Sheet

50

+VS

40

–0.5

ISHORT+

INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES

30 20 10 0 –10 –20 ISHORT– –30 –40

+125°C +85°C +25°C –40°C

–1.0 –1.5 –2.0 –2.5

+2.5 +2.0 +1.5 +1.0 +0.5

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

–VS

09730-023

–50 –40

4

6

8

10

12

14

16

18

SUPPLY VOLTAGE (±VS)

Figure 16. Short-Circuit Current vs. Temperature (G = 1)

09730-026

SHORT-CIRCUIT CURRENT (mA)

AD8429

Figure 19. Input Voltage Limit vs. Supply Voltage

30

+VS

25

SLEW RATE (V/µs)

–SR 20 +SR 15

10

5

–0.8 –1.2

+2.0 +1.6 +1.2 +125°C +85°C +25°C –40°C

+0.8 +0.4

–25

–10

5

20

35

50

65

80

95

110

125

TEMPERATURE (°C)

–VS

09730-024

0 –40

4

6

8

10

12

14

16

18


Figure 17. Slew Rate vs. Temperature, VS = ±15 V (G = 1)

09730-027

OUTPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES

–0.4

Figure 20. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ +VS

25

+SR 15

10

5

–0.8 –1.2

+2.0 +1.6 +1.2 +125°C +85°C +25°C –40°C

+0.8

–25

–10

5

20

35

50

65

80

95

110

TEMPERATURE (°C)

125

09730-025

+0.4 0 –40

–VS

4

6

8

10

12

14

16

18


Figure 21. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ

Figure 18. Slew Rate vs. Temperature, VS = ±5 V (G = 1)


09730-028

20

SLEW RATE (V/µs)

OUTPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES

–0.4 –SR

Data Sheet 15

AD8429 10

VS = ±15V

GAIN = 1000

8 6

NONLINEARITY (ppm)

OUTPUT VOLTAGE SWING (V)

10

5 +125°C +85°C +25°C –40°C

0

–5

4 2 0 –2 –4 –6

–10

100k

10k

1k LOAD (Ω)

–10 –10

09730-029

–15 100

–6

–4

–2

0

2

4

6

8

10

OUTPUT VOLTAGE (V)

Figure 25. Gain Nonlinearity (G = 1000), RL = 10 kΩ

Figure 22. Output Voltage Swing vs. Load Resistance +VS

–8

09730-084

–8

1000

VS = ±15V

–0.8

100

–1.2

G=1

NOISE (nV/√Hz)

–1.6

+2.0 +1.6

10

G = 10 G = 100

1

G = 1k

+125°C +85°C +25°C –40°C

+0.8 +0.4 –VS 10µ

100µ

1m

10m

OUTPUT CURRENT (A)

Figure 23. Output Voltage Swing vs. Output Current

0.1

1

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 26. RTI Voltage Noise Spectral Density vs. Frequency

10 GAIN = 1

8 GAIN = 1000, 100nV/DIV

4 2

GAIN = 1, 1μV/DIV

0 –2 –4

–8 –10 –10

1s/DIV

–8

–6

–4

–2

0

2

4

6

OUTPUT VOLTAGE (V)

8

10

09730-086

–6

09730-083

NONLINEARITY (ppm)

6

Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1, G = 1000)

Figure 24. Gain Nonlinearity (G = 1), RL = 10 kΩ


09730-126

+1.2

09730-030

OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES

–0.4

AD8429

Data Sheet

100

NOISE (pA/√Hz)

5V/DIV 750ns TO 0.01% 872ns TO 0.001%

10

2µs/DIV

1

10

100

1k

10k

100k

FREQUENCY (Hz)

TIME (µs)

09730-087

1

09730-090

0.002%/DIV

Figure 31. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step, VS = ±15 V

Figure 28. Current Noise Spectral Density vs. Frequency

5V/DIV 640ns TO 0.01% 896ns TO 0.001%

1s/DIV

2µs/DIV TIME (µs)


Figure 29. 0.1 Hz to 10 Hz Current Noise 30

G=1 VS = ±15V

5V/DIV

20

840ns TO 0.01% 1152ns TO 0.001%

15

10 VS = ±5V

2µs/DIV

0 100

1k

10k

100k

1M

FREQUENCY (Hz)

10M

TIME (µs)

09730-040

5

0.002%/DIV

09730-089

OUTPUT VOLTAGE (V p-p)

25

09730-091

50pA/DIV

09730-088

0.002%/DIV


Figure 30. Large Signal Frequency Response


Data Sheet

AD8429 G = 100

5V/DIV 5.04µs TO 0.01% 6.96µs TO 0.001%

TIME (µs)

Figure 37. Small Signal Response (G = 100), RL = 10 kΩ, CL = 100 pF


09730-042

1µs/DIV

10µs/DIV

20mV/DIV



09730-043

1µs/DIV


50mV/DIV

NO LOAD CL = 100pF CL = 147pF

1µs/DIV

09730-093

G=1

G = 10

20mV/DIV

09730-045

G = 1000

G=1

50mV/DIV

1µs/DIV

20mV/DIV

09730-041

10µs/DIV

09730-044

0.002%/DIV

Figure 39. Small Signal Response with Various Capacitive Loads (G = 1), RL = Infinity


AD8429

Data Sheet

1400

AMPLITUDE (Percentage of Fundamental)

1

SETTLED TO 0.001%

800

SETTLED TO 0.01% 600 400 200

2

4

6

8

10

12

14

16

18

20

STEP SIZE (V)

0.01

0.001

0.0001 10

09730-092

0

0.1

1

G = 1, SECOND HARMONIC VOUT = 10V p-p

0.1

0.01

0.001

100

1k

10k

100k

FREQUENCY (Hz)

G = 1000, THIRD HARMONIC VOUT = 10V p-p

0.1

0.01

0.001

100

1k

10k

100k

Figure 44. Third Harmonic Distortion vs. Frequency (G = 1000) 1

G = 1, THIRD HARMONIC VOUT = 10V p-p

0.1

0.01

0.01

THD (%)

0.1

0.001

VOUT = 10V p-p RL ≥ 2kΩ

GAIN = 100

0.001 GAIN = 1000

0.00001 10

100

1k

10k

100k

FREQUENCY (Hz)

0.00001 10

Figure 42. Third Harmonic Distortion vs. Frequency (G = 1)

100

1k FREQUENCY (Hz)

Figure 45. THD vs. Frequency


10k

100k

09730-100

0.0001 GAIN = 10 GAIN = 1

0.0001

09730-097


NO LOAD 2kΩ LOAD 600Ω LOAD

100k

FREQUENCY (Hz)

Figure 41. Second Harmonic Distortion vs. Frequency (G = 1) 1


0.0001 10

09730-096

0.0001

0.00001 10

10k

Figure 43. Second Harmonic Distortion vs. Frequency (G = 1000)




1k

FREQUENCY (Hz)

Figure 40. Settling Time vs. Step Size (G = 1) 1

100

09730-098

1000

G = 1000, SECOND HARMONIC VOUT = 10V p-p

09730-099

SETTLING TIME (ns)

1200


Data Sheet

AD8429

THEORY OF OPERATION VB

I

I

IB COMPENSATION A1

IB COMPENSATION

A2

C1

C2

R3 5kΩ +VS

R4 5kΩ

NODE 1

+VS

+VS

Q1

–IN

+VS

R2 3kΩ

R1 3kΩ

VOUT

A3

NODE 2 +VS

Q2

R5 5kΩ

+VS –VS

R6 5kΩ

REF

+IN

RG RG–

–VS

RG+ –VS

–VS

–VS

09730-058

–VS

Figure 46. Simplified Schematic

ARCHITECTURE

Table 5. Gains Achieved Using 1% Resistors

The AD8429 is based on the classic 3-op-amp topology. This topology has two stages: a preamplifier to provide differential amplification followed by a difference amplifier that removes the common-mode voltage and provides additional amplification. Figure 46 shows a simplified schematic of the AD8429.

1% Standard Table Value of RG 6.04 kΩ 1.5 kΩ 665 Ω 316 Ω 121 Ω 60.4 Ω 30.1 Ω 12.1 Ω 6.04 Ω 3.01 Ω

The first stage works as follows. To keep its two inputs matched, Amplifier A1 must keep the collector of Q1 at a constant voltage. It does this by forcing RG− to be a precise diode drop from –IN. Similarly, A2 forces RG+ to be a constant diode drop from +IN. Therefore, a replica of the differential input voltage is placed across the gain setting resistor, RG. The current that flows through this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. The second stage is a G = 1 difference amplifier, composed of Amplifier A3 and the R3 through R6 resistors. This stage removes the common-mode signal from the amplified differential signal. The transfer function of the AD8429 is where:

RG

Placing a resistor across the RG terminals sets the gain of the AD8429, which can be calculated by referring to Table 5 or by using the following gain equation:

6 kΩ

RG Power Dissipation

REFERENCE TERMINAL

6 kΩ

GAIN SELECTION

RG =

The AD8429 defaults to G = 1 when no gain resistor is used. Add the tolerance and gain drift of the RG resistor to the specifications of the AD8429 to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal. The AD8429 duplicates the differential voltage across its inputs onto the RG resistor. Choose an RG resistor size sufficient to handle the expected power dissipation.

VOUT = G × (VIN+ − VIN−) + VREF

G = 1+

Calculated Gain 1.993 5.000 10.02 19.99 50.59 100.3 200.3 496.9 994.4 1994

The output voltage of the AD8429 is developed with respect to the potential on the reference terminal. This is useful when the output signal must be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to level shift the output, allowing the AD8429 to drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.3 V.

G −1


AD8429

Data Sheet

For best performance, maintain a source impedance to the REF terminal that is well below 1 Ω. As shown in Figure 46, the reference terminal, REF, is at one end of a 5 kΩ resistor. Additional impedance at the REF terminal adds to this 5 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be calculated as follows: 2(5 kΩ + RREF)/(10 kΩ + RREF)

Parasitic capacitance at the gain setting pins can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), choose a component such that the parasitic capacitance is as small as possible.

Power Supplies and Grounding

Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR.

Use a stable dc voltage to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 9 and Figure 10 for more information.

CORRECT

AD8429

Place a 0.1 μF capacitor as close as possible to each supply pin. Because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. A parasitic inductance in the bypass ground trace works against the low impedance created by the bypass capacitor. As shown in Figure 49, a 10 μF capacitor can be used farther away from the device. For larger value capacitors, intended to be effective at lower frequencies, the current return path distance is less critical. In most cases, this capacitor can be shared by other precision integrated circuits.

AD8429 REF

V

V +

09730-059

OP1177 –

Figure 47. Driving the Reference Pin

INPUT VOLTAGE RANGE

+VS

Figure 4 and Figure 5 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. The 3-op-amp architecture of the AD8429 applies gain in the first stage before removing common-mode voltage with the difference amplifier stage. Internal nodes between the first and second stages (Node 1 and Node 2 in Figure 46) experience a combination of a gained signal, a common-mode signal, and a diode drop. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited.

0.1µF +IN RG

VOUT

AD8429

LOAD REF

–IN

0.1µF

LAYOUT To ensure optimum performance of the AD8429 at the PCB level, care must be taken in the design of the board layout. The pins of the AD8429 are arranged in a logical manner to aid in this task. –IN 1

8 +VS

RG 2

7 VOUT

RG 3

6 REF

AD8429

5 –VS


09730-060

+IN 4

10µF

–VS

10µF

09730-061

INCORRECT

REF

source resistance in the input path (for example, for input protection) close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the PCB traces.

Figure 49. Supply Decoupling, REF, and Output Referred to Local Ground

A ground plane layer is helpful to reduce parasitic inductances. This minimizes voltage drops with changes in current. The area of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the impedance of the path at high frequency. Large changes in currents in an inductive decoupling path or ground return create unwanted effects, due to the coupling of such changes into the amplifier inputs. Because load currents flow from the supplies, the load should be connected at the same physical location as the bypass capacitor grounds.

Figure 48. Pinout Diagram

Common-Mode Rejection Ratio over Frequency

Reference Pin

Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To maintain high CMRR over frequency, closely match the input source impedance and capacitance of each path. Place additional

The output voltage of the AD8429 is developed with respect to the potential on the reference terminal. Ensure that REF is tied to the appropriate local ground.


Data Sheet

AD8429

INPUT BIAS CURRENT RETURN PATH

Noise sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used at the inputs to shunt current away from the AD8429 inputs, thereby allowing smaller protection resistor values. To ensure current flows primarily through the external protection diodes, place a small value resistor, such as a 33 Ω, between the diodes and the AD8429.

INCORRECT

CORRECT

+VS

+VS

RPROTECT

AD8429

+ VIN+ –

AD8429 REF

I

AD8429

+

–VS

VIN– –

+VS 33Ω

RPROTECT

+VS

I

+ VIN+ –

–VS

AD8429

+VS 33Ω

RPROTECT

RPROTECT

REF

–VS

+VS

+ VIN– –

–VS –VS

–VS

TRANSFORMER

SIMPLE METHOD

TRANSFORMER

LOW NOISE METHOD

09730-066

The input bias current of the AD8429 must have a return path to ground. When using a floating source without a current return path, such as a thermocouple, create a current return path, as shown in Figure 50.

Figure 51. Protection for Voltages Beyond the Rails +VS

AD8429

Large Differential Input Voltage at High Gain If large differential voltages at high gain are expected, use an external resistor in series with each input to limit current during overload conditions. The limiting resistor at each input can be computed by using the following equation:

AD8429 REF

REF 10MΩ

–VS

 1  V DIFF − 1V R PROTECT ≥  − RG    2  I MAX 

–VS

THERMOCOUPLE

THERMOCOUPLE

+VS

Noise sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used across the inputs to shunt current away from the AD8429 inputs and, therefore, allow smaller protection resistor values.

+VS

C

C

C

R

1 fHIGH-PASS = 2πRC

AD8429 REF

+ VDIFF

REF R –VS

CAPACITIVELY COUPLED

I

AD8429

RPROTECT

CAPACITIVELY COUPLED

SIMPLE METHOD

Figure 50. Creating an Input Bias Current Return Path

I

+

– 09730-062

–VS

RPROTECT

RPROTECT

AD8429

C

VDIFF

AD8429

– RPROTECT LOW NOISE METHOD

09730-067

+VS

Figure 52. Protection for Large Differential Voltages

INPUT PROTECTION

IMAX

Do not allow the inputs of the AD8429 to exceed the ratings stated in the Absolute Maximum Ratings section of this data sheet. If this cannot be done, protection circuitry can be added in front of the AD8429 to limit the current into the inputs to a maximum current, IMAX.

The maximum current into the AD8429 inputs, IMAX, depends on time and temperature. At room temperature, the device can withstand a current of 10 mA for at least one day. This time is cumulative over the life of the device.

Input Voltages Beyond the Rails If voltages beyond the rails are expected, use an external resistor in series with each input to limit current during overload conditions. The limiting resistor at the input can be computed from R PROTECT ≥

| VIN − VSUPPLY | I MAX

RADIO FREQUENCY INTERFERENCE (RFI) RF rectification is often a problem when amplifiers are used in applications that have strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 53.


AD8429

Data Sheet +VS 0.1µF

L*

10µF

CC 1nF

Source Resistance Noise

R

+IN

33Ω L*

at the amplifier input. To calculate the noise referred to the amplifier output (RTO), simply multiply the RTI noise by the gain of the instrumentation amplifier.

CD 10nF

AD8429

R

Any sensor connected to the AD8429 has some output resistance. There may also be resistance placed in series with inputs for protection from either overvoltage or radio frequency interference. This combined resistance is labeled R1 and R2 in Figure 54. Any resistor, no matter how well made, has an intrinsic level of noise. This noise is proportional to the square root of the resistor value. At room temperature, the value is approximately equal to 4 nV/√Hz × √(resistor value in kΩ).

OUT REF

–IN

33Ω CC 1nF

0.1µF

09730-049

10µF –VS

*CHIP FERRITE BEAD.

Figure 53. RFI Suppression

The filter limits the input signal bandwidth, according to the following relationship: FilterFrequency DIFF FilterFrequency CM

1  2πR(2C D  CC )

CD affects the difference signal, and CC affects the common-mode signal. Choose values of R and CC that minimize RFI. A mismatch between R × CC at the positive input and R × CC at the negative input degrades the CMRR of the AD8429. By using a value of CD that is one magnitude larger than CC, the effect of the mismatch is reduced, and performance is improved. Resistors add noise; therefore, the choice of resistor and capacitor values depends on the desired tradeoff between noise, input impedance at high frequencies, and RFI immunity. The resistors used for the RFI filter can be the same as those used for input protection.

CALCULATING THE NOISE OF THE INPUT STAGE SENSOR

2

 64  16  8.9 nV/√Hz

Total Voltage Noise =

Output Noise / G 2  Input Noise 2  Noise of RG Resistor 2 For example, for a gain of 100, the gain resistor is 60.4 Ω. Therefore, the voltage noise of the in-amp is

45 / 100 2  12  4  0.0604  = 1.5 nV/√Hz 2

Current Noise of the Instrumentation Amplifier Current noise is calculated by multiplying the source resistance by the current noise. For example, if the R1 source resistance in Figure 54 is 4 kΩ, and the R2 source resistance is 1 kΩ, the total effect from the current noise is calculated as follows:

4  1.52  1  1.52  = 6.2 nV/√Hz

AD8429

Total Noise Density Calculation

09730-064

R2

2

The voltage noise of the instrumentation amplifier is calculated using three parameters: the device input noise, output noise, and the RG resistor noise. It is calculated as follows:

where CD  10 CC.

R1

4  4   4  1 

Voltage Noise of the Instrumentation Amplifier

1  2πRC C

RG

For example, assuming that the combined sensor and protection resistance on the positive input is 4 kΩ, and on the negative input is 1 kΩ, the total noise from the input resistance is

Figure 54. Source Resistance from Sensor and Protection Resistors

The total noise of the amplifier front end depends on much more than the 1 nV/√Hz specification of this data sheet. There are three main contributors: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier.

To determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method. For example, if the R1 source resistance in Figure 54 is 4 kΩ, the R2 source resistance is 1 kΩ, and the gain of the in-amps is 100, the total noise, referred to input, is

In the following calculations, noise is referred to the input (RTI). In other words, everything is calculated as if it appeared


8.9 2  1.5 2  6.2 2 = 11.0 nV/√Hz

Data Sheet

AD8429

OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890)

8 1

5 4

1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE

6.20 (0.2441) 5.80 (0.2284)

1.75 (0.0688) 1.35 (0.0532)

0.51 (0.0201) 0.31 (0.0122)

0.50 (0.0196) 0.25 (0.0099)

45°

8° 0° 0.25 (0.0098) 0.17 (0.0067)

1.27 (0.0500) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

012407-A

4.00 (0.1574) 3.80 (0.1497)

Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)

ORDERING GUIDE Model1 AD8429ARZ AD8429ARZ-R7 AD8429BRZ AD8429BRZ-R7 1

Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C

Package Description 8-Lead SOIC_N 8-Lead SOIC_N, 7” Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 7” Tape and Reel

Z = RoHS Compliant Part.


Package Option R-8 R-8 R-8 R-8

AD8429

Data Sheet

NOTES

©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09730-0-2/17(A)


√Hz Low Noise Instrumentation Amplifier Data Sheet AD8429

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