LTC4357 Positive High Voltage Ideal Diode Controller Features
Description
Reduces Power Dissipation by Replacing a Power Schottky Diode with an N-Channel MOSFET n 0.5µs Turn-Off Time Limits Peak Fault Current n Wide Operating Voltage Range: 9V to 80V n Smooth Switchover without Oscillation n No Reverse DC Current n Available in 6-Lead (2mm × 3mm) DFN and 8-Lead MSOP Packages
The LTC®4357 is a positive high voltage ideal diode controller that drives an external N-channel MOSFET to replace a Schottky diode. When used in diode-OR and high current diode applications, the LTC4357 reduces power consumption, heat dissipation, voltage loss and PC board area.
n
Applications n n n n n
N + 1 Redundant Power Supplies High Availability Systems AdvancedTCA Systems Telecom Infrastructure Automotive Systems
The LTC4357 easily ORs power sources to increase total system reliability. In diode-OR applications, the LTC4357 controls the forward voltage drop across the MOSFET to ensure smooth current transfer from one path to the other without oscillation. If the power source fails or is shorted, a fast turn-off minimizes reverse current transients. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application 48V, 10A Diode-OR
Power Dissipation vs Load Current 6
FDB3632
VINA 48V IN
GATE LTC4357
OUT VDD
VOUT TO LOAD
GND
DIODE (MBR10100) 4 3 2
FET (FDB3632) 0
IN
GATE LTC4357
POWER SAVED
1
FDB3632
VINB 48V
POWER DISSIPATION (W)
5
OUT
0
2
4 6 CURRENT (A)
8
10 4357 TA01b
VDD
GND 4357 TA01
*SEE FIGURES 2 AND 3 FOR ADDITIONAL OPTIONAL COMPONENTS
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LTC4357 Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltages IN............................................................. –1V to 100V OUT, VDD............................................... –0.3V to 100V Output Voltage GATE (Note 3)......................... VIN – 0.2V to VIN + 10V
Operating Ambient Temperature Range LTC4357C................................................. 0°C to 70°C LTC4357I.............................................. –40°C to 85°C LTC4357H........................................... –40°C to 125°C LTC4357MP........................................ –55°C to 125°C Storage Temperature Range.................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS Package....................................................... 300°C
pin Configuration TOP VIEW
IN 2
TOP VIEW
6 VDD
OUT 1 7 GND
IN NC NC GATE
5 NC 4 GND
GATE 3
1 2 3 4
8 7 6 5
OUT VDD NC GND
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 163°C/W
DCB PACKAGE 6-LEAD (2mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 90°C/W EXPOSED PAD (PIN 7) PCB GND CONNECTION OPTIONAL
ORDER INFORMATION LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4357CMS8#PBF
LTC4357CMS8#TRPBF
LTCXD
8-Lead Plastic MSOP
0°C to 70°C
LTC4357IMS8#PBF
LTC4357IMS8#TRPBF
LTCXD
8-Lead Plastic MSOP
–40°C to 85°C
LTC4357HMS8#PBF
LTC4357HMS8#TRPBF
LTCXD
8-Lead Plastic MSOP
–40°C to 125°C
LTC4357MPMS8#PBF
LTC4357MPMS8#TRPBF
LTFWZ
8-Lead Plastic MSOP
–55°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4357MPMS8
LTC4357MPMS8#TR
LTFWZ
8-Lead Plastic MSOP
–55°C to 125°C
LEAD FREE FINISH TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4357CDCB#TRMPBF
LTC4357CDCB#TRPBF
LCXF
6-Lead (2mm × 3mm) Plastic DFN
0°C to 70°C
LTC4357IDCB#TRMPBF
LTC4357IDCB#TRPBF
LCXF
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4357HDCB#TRMPBF
LTC4357HDCB#TRPBF
LCXF
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4357fd
LTC4357 Electrical Characteristics
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VOUT = VDD, VDD = 9V to 80V unless otherwise noted. SYMBOL
PARAMETER
CONDITIONS
MIN
VDD
Operating Supply Range
l
IDD
Supply Current
l
IIN
IN Pin Current
VIN = VOUT ±1V
l
IOUT
OUT Pin Current
VIN = VOUT ±1V
l
DVGATE
External N-Channel Gate Drive (VGATE – VIN)
VDD, VOUT = 20V to 80V VDD, VOUT = 9V to 20V
l l
IGATE(UP)
External N-Channel Gate Pull-Up Current VGATE = VIN, VIN – VOUT = 0.1V
IGATE(DOWN)
External N-Channel Gate Pull-Down Current in Fault Condition
tOFF
Gate Turn-Off Time
– VIN – VOUT = 55mV |––1V, VGATE – VIN < 1V, CGATE = 0pF
DVSD
Source-Drain Regulation Voltage (VIN – VOUT)
VGATE – VIN = 2.5V
VGATE = VIN + 5V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
TYP
MAX
9
80
UNITS V
0.5
1.25
mA
350
500
µA
80
210
µA
10 4.5
12 6
15 15
V V
l
–14
–20
–26
µA
l
1
2
150
l
10
l
A
300
500
ns
25
55
mV
Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a minimum of 10V above IN or 100V above GND. Driving this pin to voltages beyond this clamp may damage the device.
Typical Performance Characteristics VDD Current (IDD vs VDD) 800
IN Current (IIN vs VIN) 400
VDD = VOUT = VIN ± 1V
VDD = VOUT = VIN + 1V
OUT Current (IOUT vs VOUT)
150
VDD = VOUT = VIN – 1V
300
600
180
VDD = VOUT = VIN + 1V
400
IOUT (µA)
IIN (µA)
IDD (µA)
120 200
90 60
100
200
VDD = VOUT = VIN – 1V 30
0
0
20
40 VDD (V)
60
80 4357 G01
0
0
20
40 VIN (V)
60
80 4357 G02
0
0
20
40 VOUT (V)
60
80 4357 G03
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LTC4357 Typical Performance Characteristics 15
$VGATE = 2.5V
0
DVGATE vs GATE Current (DVGATE vs IGATE)
OUT Current (IOUT vs VIN) 125
VIN > 18V
100
VIN = 12V
75
VOUT = 12V, VIN = VDD
IGATE (µA)
$VGATE (V)
10
–25
IOUT (µA)
25
GATE Current vs Forward Drop (IGATE vs DVSD)
VIN = 9V
50
5 25
–50 –50
0
50 VSD (mV)
100
0
150
0
5
10 15 IGATE (µA)
20
4357 G04
500
0
25
0
2
8 6 VIN (V)
4
10
12
14 4357 G06
4357 G05
FET Turn-Off Time vs GATE Capacitance
FET Turn-Off Time vs Initial Overdrive 400
VGATE < VIN + 1V $VSD = 55mV –1V
400
VIN = 48V $VSD = VINITIAL –1V
300
tPD (ns)
tOFF (ns)
300
200
100
100 0
200
0
20
40
60
0
80
0
0.2
0.6 0.4 VINITIAL (V)
CGATE (nF) 4357 G07
FET Load Current vs DVSD 10
VIN = 48V $VSD = 55mV VFINAL
VIN = 48V WITH FET (FDB3632)
8
tPD (ns)
LOAD CURRENT (A)
1500
1000
500
0
1.0 4357 G08
FET Turn-Off Time vs Final Overdrive 2000
0.8
6
4
2
–1
–0.8
–0.4 –0.6 VFINAL (V)
–0.2
0
0
0
50
25 ∆VSD (mV)
75 4357 G10
4357 G09
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LTC4357 Pin Functions Exposed Pad: Exposed pad may be left open or connected to GND. GATE: Gate Drive Output. The GATE pin pulls high, enhancing the N-channel MOSFET when the load current creates more than 25mV of voltage drop across the MOSFET. When the load current is small, the gate is actively driven to maintain 25mV across the MOSFET. If reverse current develops more than –25mV of voltage drop across the MOSFET, a fast pull-down circuit quickly connects the GATE pin to the IN pin, turning off the MOSFET.
is used to control the source-drain voltage across the MOSFET. The GATE fast pull-down current is returned through the IN pin. Connect this pin as close as possible to the MOSFET source. NC: No Connection. Not internally connected.
GND: Device Ground.
OUT: Drain Voltage Sense. OUT is the cathode of the ideal diode and the common output when multiple LTC4357s are configured as an ideal diode-OR. It connects to the drain of the N-channel MOSFET. The voltage sensed at this pin is used to control the source-drain voltage across the MOSFET.
IN: Input Voltage and GATE Fast Pull-Down Return. IN is the anode of the ideal diode and connects to the source of the N-channel MOSFET. The voltage sensed at this pin
VDD: Positive Supply Input. The LTC4357 is powered from the VDD pin. Connect this pin to OUT either directly or through an RC hold-up circuit.
block diagram IN
OUT
GATE
17V
CHARGE PUMP VDD
+
+
– 25mV
FPD COMP
+ –
GATE AMP
– + –
IN
25mV
GND 4357 BD
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LTC4357 Operation High availability systems often employ parallel-connected power supplies or battery feeds to achieve redundancy and enhance system reliability. ORing diodes have been a popular means of connecting these supplies at the point of load. The disadvantage of this approach is the forward voltage drop and resulting efficiency loss. This drop reduces the available supply voltage and dissipates significant power. Using an N-channel MOSFET to replace a Schottky diode reduces the power dissipation and eliminates the need for costly heat sinks or large thermal layouts in high power applications. The LTC4357 controls an external N-channel MOSFET to form an ideal diode. The voltage across the source and drain is monitored by the IN and OUT pins, and the GATE pin drives the MOSFET to control its operation. In effect the MOSFET source and drain serve as the anode and cathode of an ideal diode. At power-up, the load current initially flows through the body diode of the MOSFET. The resulting high forward
voltage is detected at the IN and OUT pins, and the LTC4357 drives the GATE pin to servo the forward drop to 25mV. If the load current causes more than 25mV of voltage drop when the MOSFET gate is driven fully on, the forward voltage is equal to RDS(ON) • ILOAD. If the load current is reduced causing the forward drop to fall below 25mV, the MOSFET gate is driven lower by a weak pull-down in an attempt to maintain the drop at 25mV. If the load current reverses and the voltage across IN to OUT is more negative than –25mV the LTC4357 responds by pulling the MOSFET gate low with a strong pull-down. In the event of a power supply failure, such as if the output of a fully loaded supply is suddenly shorted to ground, reverse current temporarily flows through the MOSFET that is on. This current is sourced from any load capacitance and from the other supplies. The LTC4357 quickly responds to this condition turning off the MOSFET in about 500ns, thus minimizing the disturbance to the output bus.
Applications Information MOSFET Selection
ORing Two-Supply Outputs
The LTC4357 drives an N-channel MOSFET to conduct the load current. The important features of the MOSFET are on-resistance, RDS(ON), the maximum drain-source voltage, VDSS, and the gate threshold voltage.
Where LTC4357s are used to combine the outputs of two power supplies, the supply with the highest output voltage sources most or all of the load current. If this supply’s output is quickly shorted to ground while delivering load current, the flow of current temporarily reverses and flows backwards through the LTC4357’s MOSFET. When the reverse current produces a voltage drop across the MOSFET of more than –25mV, the LTC4357’s fast pull-down activates and quickly turns off the MOSFET.
Gate drive is compatible with 4.5V logic-level MOSFETs in low voltage applications (VDD = 9V to 20V). At higher voltages (VDD = 20V to 80V) standard 10V threshold MOSFETs may be used. An internal clamp limits the gate drive to 15V between the GATE and IN pins. An external Zener clamp may be added between GATE and IN for MOSFETs with a VGS(MAX) of less than 15V. The maximum allowable drain-source voltage, BVDSS, must be higher than the power supply voltage. If an input is connected to GND, the full supply voltage will appear across the MOSFET.
If the other, initially lower, supply was not delivering load current at the time of the fault, the output falls until the body diode of its ORing MOSFET conducts. Meanwhile, the LTC4357 charges its MOSFET gate with 20µA until the forward drop is reduced to 25mV. If instead this supply was delivering load current at the time of the fault, its associated ORing MOSFET was already driven at least partially on, and the LTC4357 will simply drive the MOSFET gate harder in an effort to maintain a drop of 25mV. 4357fd
LTC4357 Applications Information Load Sharing
Input Short-Circuit Faults
The application in Figure 1 combines the outputs of multiple, redundant supplies using a simple technique known as droop sharing. Load current is first taken from the highest output, with the low outputs contributing as the output voltage falls under increased loading. The 25mV regulation technique ensures smooth load sharing between outputs without oscillation. The degree of sharing is a function of RDS(ON), the output impedance of the supplies and their initial output voltages.
The dynamic behavior of an active, ideal diode entering reverse bias is most accurately characterized by a delay followed by a period of reverse recovery. During the delay phase some reverse current is built up, limited by parasitic resistances and inductances. During the reverse recovery phase, energy stored in the parasitic inductances is transferred to other elements in the circuit. Current slew rates during reverse recovery may reach 100A/µs or higher.
M1 FDB3632
VINA 48V
48V BUS
PSA RTNA
IN
GATE LTC4357
OUT VDD
GND
M2 FDB3632
VINB 48V PSB RTNB
IN
GATE LTC4357
OUT VDD
GND
M3 FDB3632
VINC 48V PSC RTNC
IN
GATE LTC4357
OUT VDD
GND 4357 F01
Figure 1. Droop Sharing Redundant Supplies
High slew rates coupled with parasitic inductances in series with the input and output paths may cause potentially destructive transients to appear at the IN and OUT pins of the LTC4357 during reverse recovery. A zero impedance short-circuit directly across the input of the circuit is especially troublesome because it permits the highest possible reverse current to build up during the delay phase. When the MOSFET finally commutates the reverse current the LTC4357 IN pin experiences a negative voltage spike, while the OUT pin spikes in the positive direction. To prevent damage to the LTC4357 under conditions of input short-circuit, protect the IN pin and OUT pin as shown in Figure 2. The IN pin is protected by clamping to the GND pin in the negative direction. Protect the OUT pin with a clamp, such as with a TVS or TransZorb, or with a local bypass capacitor of at least 10µF. In low voltage applications the MOSFET's drain-source breakdown may be sufficient to protect the OUT pin, provided BVDSS + VIN < 100V. Parasitic inductance between the load bypass and the LTC4357 allows a zero impedance input short to collapse the voltage at the VDD pin, which increases the total turn-off time (tOFF). For applications up to 30V, bypass the VDD pin with 39µF; above 30V use at least 100µF. If VDD is powered from the output side, one capacitor serves to guard against VDD collapse and also protect OUT from voltage spikes. If the OUT pin is protected by a diode clamp or if VDD is powered from the input side, decouple the VDD pin with a separate 100Ω, 100nF filter (see Figure 3). In applications above 10A increase the filter capacitor to 1µF.
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LTC4357 Applications Information INPUT PARASITIC INDUCTANCE VIN
+
–
INPUT SHORT
OUTPUT PARASITIC INDUCTANCE
REVERSE RECOVERY CURRENT
+
M1
IN
DIN SBR1U150SA
GATE
OUT COUT 10µF
VDD
LTC4357
OR
–
VOUT
DCLAMP SMAT70A
CLOAD
GND 4357 F02
Figure 2. Reverse Recovery Produces Inductive Spikes at the IN and OUT Pin. The Polarity of Step Recovery Spikes is Shown Across Parasitic Inductances OUTPUT PARASITIC INDUCTANCE
M1
VIN
INPUT SHORT
IN
GATE
OUT
LTC4357
VOUT
R1 100Ω COUT
OR
VDD
CLOAD
C1 100nF
GND 4357 F03
Figure 3. Protecting Against Collapse of VDD During Reverse Recovery
Design Example The following design example demonstrates the calculations involved for selecting components in a 12V system with 10A maximum load current (see Figure 4).
M1 Si4874DY
VIN1 12V
IN
First, calculate the RDS(ON) of the MOSFET to achieve the desired forward drop at full load. Assuming VDROP = 0.1V, RDS(ON) ≤
VDROP I LOAD
=
The Si4874DY offers a good solution, in an S8 package with RDS(ON) = 10mΩ(max) and BVDSS of 30V. The maximum power dissipation in the MOSFET is:
LTC4357
P = ILOAD2 • RDS(ON) = (10A)2 • 10mW = 1W
With less than 39µF of local bypass, the recommended RC values of 100W and 0.1µF were used in Figure 4.
OUT
R1 100Ω
VDD C1 0.1µF
GND
0.1V 10A
RDS(ON) ≤ 10mΩ
GATE
VOUT TO LOAD
M2 Si4874DY
VIN2 12V
IN
GATE LTC4357
OUT
R1 100Ω
VDD C1 0.1µF
GND 4357 F04
Figure 4. 12V, 10A Diode-OR
Since BVDSS + VIN is much less than 100V, output clamping is unnecessary. 4357fd
LTC4357 Applications Information Layout Considerations Connect the IN and OUT pins as close as possible to the MOSFET’s source and drain pins. Keep the traces to the MOSFET wide and short to minimize resistive losses. See Figure 5.
VIN
1 S
D 8
2 S
D 7
3 S 4 G
MOSFET
For the DFN package, pin spacing may be a concern at voltages greater than 30V. Check creepage and clearance guidelines to determine if this is an issue. To increase the pin spacing between high voltage and ground pins, leave the exposed pad connection open. Use no-clean solder to minimize PCB contamination.
1 S
D 8
2 S
D 7
D 6
3 S
D 6
D 5
4 G
D 5
OUT
6
4357 F05
7
GATE
1
LTC4357
VOUT
IN GATE
3
OUT
VIN
2
IN
VOUT
5
4
Figure 5. Layout Considerations
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LTC4357 Typical Applications Solar Panel Charging a Battery M1 FDB3632
14V SHUNT REGULATOR
100W SOLAR PANEL
R1 100Ω
IN
GATE
VDD
OUT
+
LTC4357
C1 0.1µF
12V BATTERY
LOAD
GND 4357 TA02
–12V Reverse Input Protection
–48V Reverse Input Protection
M1 Si4874DY
VIN 12V
CLOAD IN
GATE
VOUT 12V 10A
CLOAD IN
OUT
LTC4357
M1 FDB3632
VIN 48V
GATE LTC4357
VDD
OUT VDD DCLAMP SMAT70A
GND
GND D1 MMBD1205
4357 TA03
D1 MMBD1205
VOUT 48V 10A
4357 TA04
Low Current Shutdown M1 FDS3672
VIN 48V 5A
VOUT DCLAMP SMAT70A
10M R1 100Ω
IN VDD
C1 0.1µF
GATE
OUT
LTC4357 GND 4357 TA05
ON OFF
G1 BSS123
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10
LTC4357 Package Description DCB Package 6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
R = 0.115 TYP
2.00 p0.10 (2 SIDES)
R = 0.05 TYP
0.70 p0.05
3.55 p0.05
1.65 p0.05 (2 SIDES)
3.00 p0.10 (2 SIDES)
0.40 p 0.10 4
6
1.65 p 0.10 (2 SIDES)
2.15 p0.05 PACKAGE OUTLINE
PIN 1 NOTCH R0.20 OR 0.25 s 45o CHAMFER
PIN 1 BAR TOP MARK (SEE NOTE 6) 3
0.25 p 0.05 0.50 BSC 1.35 p0.05 (2 SIDES)
0.200 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.75 p0.05
1
(DCB6) DFN 0405
0.25 p 0.05 0.50 BSC
1.35 p0.10 (2 SIDES) 0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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11
LTC4357 Package Description MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 p 0.102 (.118 p .004) (NOTE 3)
0.889 p 0.127 (.035 p .005)
5.23 (.206) MIN
0.254 (.010)
7 6 5
0.52 (.0205) REF
3.00 p 0.102 (.118 p .004) (NOTE 4)
4.90 p 0.152 (.193 p .006)
DETAIL “A” 0o – 6o TYP
GAUGE PLANE
3.20 – 3.45 (.126 – .136)
0.53 p 0.152 (.021 p .006) DETAIL “A”
0.42 p 0.038 (.0165 p .0015) TYP
8
0.65 (.0256) BSC
1 1.10 (.043) MAX
2 3
4 0.86 (.034) REF
0.18 (.007)
RECOMMENDED SOLDER PAD LAYOUT NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
SEATING PLANE
0.22 – 0.38 (.009 – .015) TYP
0.65 (.0256) BSC
0.1016 p 0.0508 (.004 p .002) MSOP (MS8) 0307 REV F
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12
LTC4357 Revision History
(Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
09/10
Revised θJA value for MS8 package in Pin Configuration section and added MP-grade to Order Information section Added two new plots and revised remaining curves in Typical Performance Characteristics section
2 3, 4
Updated Electrical Characteristics section
4
Revised Figure 2 and Figure 4 in Applications Information section
8
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
13
LTC4357 Typical Application Plug-In Card Input Diode for Supply Hold-Up BACKPLANE PLUG-IN CARD CONNECTORS CONNECTOR 1
FDB3632
48V
IN
GATE LTC4357
Hot Swap CONTROLLER
VOUT1
OUT
+
VDD
CHOLDUP
SMAT70A
GND
GND FDB3632
IN
GATE LTC4357
Hot Swap CONTROLLER
VOUT2
OUT
+
VDD
CHOLDUP
SMAT70A
GND
GND GND
PLUG-IN CARD CONNECTOR 2
4357 TA06
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14 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507
l
www.linear.com
LT 0910 REV D • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2007
