Shallow Junctions Contacts - web.stanford.edu

Shallow Junctions & Contacts Prof. Krishna Saraswat Department of Electrical Engineering Stanford University Stanford, CA 94305 [email protected]

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Saraswat / EE311 / Shallow Junctions

Outline •Junction/contact scaling issues •Shallow junction technology •Ohmic contacts •Technology to form contacts

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MOS Device Scaling Constant E Field Scaling All device parameters are scaled by the same factor. • gate oxide thickness xox ↓ • channel length L ↓ • source/drain junction depth Xj ↓ • Channel doping ↑ • Supply voltage VDD ↓

L xox

Xj L

N+

xox

N+

Na

N+

Xj

N+

Na

lo

lo

P

P

Why do we scale MOS transistors? 1.

Increase device packing density

2.

Improve frequency response α 1/L

3.

Improve current drive (transconductance gm)

gm =

" ID "VG VD = const

W µn L W # µ L n #

Kox VD for VD < VD SAT , linear region to x Kox (VG $ VT ) for VD > VDSAT , saturation region to x

Why do we need to scale junction depth? Stanford University

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Short Channel Effects on Threshold voltage Ddepletion width in a long channel device

W=

2" (2# F + VBG ) qN A

Gate

We can approximate, the bulk charge as #L + L Q B " L = q " N A " W " %% $ 2

'

!

& (( '

N+ source

L Depletion region L!

N+ drain rj

P-Si

By trigonometry, we can write:

QB depleted by source

QB depleted by drain

$ ' r L + L' 2#W j = 1" && 1 + "1)) # 2L rj % ( L

We can then approximate the threshold voltage as:

Q * $ 2 " W ' rj VT = VFB ! 2 " # F ! B " ,1 ! & 1+ ! 1) " / Cox + % rj ( L.

Threshold voltage is a function of junction depth, depletion width and channel length? L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974

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Need for Shallow Source/Drain Junctions

Q * $ 2 " W ' rj VT = VFB ! 2 " # F ! B " ,1 ! & 1+ ! 1) " / Cox rj ( L. + %

• Roll-off in threshold voltage as the channel length is reduced and drain voltage is increased • To minimimize VT roll-off •Reduce as junction depth(rj) •Increase in Cox should increase gate control Sheet resistance increases as junction depth is reduced Stanford University

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Source/drain Junction Depth

Year Min Feature Size Contact xj (nm) xj at Channel (nm)

1997 0.25! 100-200 50-100

1999 0.18! 70-140 36-72

2003 0.13! 50-100 26-52

2006 0.10! 40-80 20-40

2009 0.07! 15-30 15-30

2012 0.05! 10-20 10-20

From the ITRS roadmap

• Source/drain doping requirements show continuing drive to obtain shallow junctions. • How will we form such shallow junctions? • How will we make low resistance contacts to them? • How will we minimize the sheet resistance of the junctions? Stanford University

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Lch t ox ⇒ Scaled with Lg Rch " (V gs ! Vth ) (Lch ↓, tox↓) 1 Rsd ! Rsh ! N sd X j

70

2001 ITRS Physical Gate Length

60 50

50

Max. Ratio of R sd to Ideal R ch40

40

30

30

20

20 10 0 2000

60

10

SDE Junction Depth 2004

⇒ Difficult to scale (Nsd const, Xj↓) ⇒ Rsd/Rch ↑

2008

Year

2012

2016

Rsd/Rch-ideal [%]

Gate Length or SDE Depth [nm]

S/D Junction Scaling Trend

0

Ref: J. Woo (UCLA)

• As Lg scales down, Rsd becomes comparable to Rch • Rsd becomes important factor for device current • Parasitic portion of the device is now playing important role in device performance and CMOS scaling Stanford University

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Sidewall

Gate

Silicide

Rcsd

Rdp

Rext

Rov

Nov(y)

x

Series Resistance (ohms)

y=0

140

Relative Contribution [%]

Impact of Parasitic Series Resistance

70

Next(x)

Problem in junction scaling: • Sheet resistance of a junction is a strong function of doping density • Maximum doping density is limited by solid solubility and it does not scale ! • Silicidation can minimize the impact of junction sheet resistance • Contact resistance R csd is one of the dominant components for future technology Source: Jason Woo, UCLA Stanford University

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120 NMOS 100

Scaled by ITRS Roadmap

80

Rext

60

Rdp Rcsd

40 20 0

60 50 40 30 20

Rov

30 nm 50 nm 70 nm 100 nm Physical Gate Length

NMOS

Rcsd Rext Rov

10 0

Rdp 32 nm 53 nm 70 nm 100 nm Physical Gate Length


Relative Contribution [%]

Series Resistance (ohms)

Relative Contributions of Resistance Components: PMOSFETs 200 PMOS

Scaled by ITRS Roadmap

150

Rov

100

Rext

50

Rdp Rcsd

0

30 nm 50 nm 70 nm 100 nm

70

Rcsd

60

PMOS

50 40 30 20 10

Physical Gate Length

0

Rov Rext

Rdp

32 nm 53 nm 70 nm 100 nm Physical Gate Length

• Problem even more serious for PMOS • Rcsd will be a dominant component for highly scaled nanometer transistor ( Rcsd/Rseries ↑ >> ~ 60 % for LG < 53 nm) Source: Jason Woo, UCLA Stanford University

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Dopant Diffusion Ion Implant Gate Stack Anneal/Diffusion

• Solutions to diffusion equations (Fick's laws) gives bulk diffusivity Di = D io " e

_ EO

k"T

• In shallow junction technologies, numerous effects alter these values resulting in enhanced diffusion. • Transient enhanced diffusion D = Di + D o " e

_t

#

• Diffusion affected by defects, e.g.,oxidation induced point defects

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Diffusion Affected by Oxidation Induced Point Defects TSUPREM IV simulations of oxidation enhanced diffusion of boron (OED) and oxidation retarded diffusion of antimony (ORD) during the growth of a thermal oxide on the surface of silicon.

!

antimony boron

Oxidation increases interstitials (CI) and decreases vacancies (CV) from their equilibrium values. This in turn changes diffusivity. (Ref: Plummer, et al., Silicon VLSI Technology - Fundamentals, Practice and Models)

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Diffusion in Polycrystalline Materials

DGB grain boundary diffusion DL lattice diffusion Generally DGB >> DL

The worst-case demonstration of the defect enhanced diffusion of dopants is in polycrystalline silicon, which can be several times faster than diffusion in bulk Si because of defects at the grain boundaries.

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Transient Enhanced Diffusion (TED) 40 keV, 10-14 cm-2 B 750ºC anneal

τ

At lower temperatures, the damage can stay around longer and enhance the dopant diffusion, while at higher temperatures the damage annihilates faster. Thus the diffusivity is a function of time during the transient.

% t( D = Di + Do " exp'# * & $)

Where

# E & Di = Dio exp%" 0 ( is intrinsic diffusity $ kT '

Ref: Plummer, et.al.,

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14

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Effect of TED on Junction Depth

• At lower temperature longer times are needed to anneal the damage • Transient enhanced dopant diffusion effects are stronger • Junction depth is larger • Higher temperature and shorter times are needed to minimize TED

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Shallow Junction Formation Technologies Low Energy Implantation 12 keV B implants Concentration (cm-3)

Concentration (cm-3)

40 keV As and B implants

Boron Arsenic

Boron

BF2

Depth

As Concentration (cm-3)

Depth

) -3

1022 10

m c ( 1018 s A 1016

Stanford University

as-implanted

20

5 keV 1 keV

0

20 40 60 Depth (nm)

Ref. Kasnavi, PhD Thesis Stanford Univ. 2001

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Ion Implantation Damage Heavy ions (As, P) Higher energy

Light ions (B) Lower energy

• Heavy ions (As, P) cause excessive damage turning implanted region into amorphous • Light ions (B) have buried damage

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Ion Implantation Damage Anneal Light ions (B) Lower energy

Heavy ions (As, P) Higher energy Amorphous

After implant

regrowth Crystalline SPE

After anneal

fully annealed

Buried damage

• Fully amorphized region can be fully annealed through solid phase regrowth • Buried damage leaves defects where damage was created as regrowth takes place both from top and bottom. Stanford University

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Log concentration (cm-3)

Pre-amorphization implants

Implanted

10 sec 1000°C RTA Ge preamorphized Si preamorphized Not preamorphized

Depth (nm)

Pre-amorphization implants can reduce the damage and yet get shallow junctions Stanford University

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B Concentration (cm-3)

Solid Source Diffusion

Depth (nm)

In COSi2

Depth (nm)

In Si after silicide removal

Boron profiles after diffusion at 950°C of 50 nm COSi2 implanted with 5 X 1015 cm-2 BF2 (a) and (b)in Si after silicide removal. Stanford University

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Gas Immersion Laser Doping (GILD)

Si wafer showing the adsorption of the dopant species onto the clean silicon surface. The dopant is incorporated into a very shallow region upon exposure to the excimer laser pulse.

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Junction Depth Vs. Sheet Resistance Tradeoff 60

Junction Depth (nm)

5 keV limit

Roadmap Y=2000, L g=180nm

50 40 1 keV limit

) m 30 n ( j X

2002, 130nm 2005, 100nm

20

2008, 70nm 2011, 50nm

10 0

2014, 35nm

0

250

500 Rs ( ! / )

1020C spike 750

1000

Ref. Kasnavi, PhD Thesis Stanford Univ. 2001

It will be difficult to meet the ITRS scaling requirments of junction depth and sheet resistance Stanford University

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Solutions to Shallow Junction Resistance Problem

Extension implants

Elevated source/ drain

Schottky Source/Drain

Silicidation Stanford University

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Effect of Scaling of Contacts and Junctions R (total) = Rch + Rparasitic Rparasitic = Rextension + Rextrinsic Rextension = Rd’ + Rs’ Rextrinsic = Rd + Rs + 2Rc Ref: Ohguro, et al., ULSI Science and Technology 1997, Electrochemical Soc. Proc., Vol. 97-3

Silicidation of junctions is necessary to minimize the impact of junction parasitic resistance Stanford University

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Elevated S/D Technology

From A. Hokazono et al (Toshiba), IEDM2000 Rcsd

•

&L # ' = c coth $ con ! LT % LT "

& q( b ) c ' exp$ $ N if %

!c

LT =

R sh ,dp

# ! ! "

Elevated S/D structure ⇒ Reduction of Rcsd by increasing Nif & reducing Rsh,dp underneath silicide

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New Structures and Materials for Nanoscale MOSFETs (From Handout #1) 5 3

4 2

Top Gate

G C

S

D

Si

Source

SiO2

1

High µ channel

Si

BULK

Drain

Bottom Gate

High-K Double gate

SOI

1. Electrostatics - Double Gate - Retain gate control over channel - Minimize OFF-state drain-source leakage

2. Transport - High Mobility Channel - High mobility/injection velocity - High drive current for low intrinsic delay

3. Parasitics - Schottky S/D - Reduced extrinsic resistance 4. Gate leakage - High-K dielectrics - Reduced power consumption 5. Gate depletion - Metal gate Stanford University

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Effect of Extrinsic Resistance on Double Gate MOSFETs Id = K⋅ K⋅(Vg–Vth–IdRs)α

1.E+21

GATE

Net Doping (cm-3)

1.E+20 1.E+19 1.E+18 1.E+17

Doping gradient

1.E+16

5nm/dec 4nm/dec 3nm/dec 2nm/dec 1nm/dec 0.5nm/dec

1.E+15 1.E+14 1.E+13 40

45

50

55

60

65

x (nm)

• Extrinsic resistance reduces gate overdrive ⇒ performance limiter in ballistic FETs • Ideally need very low specific contact resistivity and hyperabrupt lateral junctions • For a given doping abruptness: –Too much underlap ⇒ dopants spill into channel ⇒ worse SCE –Too little underlap ⇒ large series resistance in extension tip •Extrinsic (S/D) resistance may limit performance in future ultrathin body DGFETs Shenoy and Saraswat, IEEE Trans. Nanotechnology, Dec. 2003 Stanford University

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Two kinds of transistors Schottky S/D MOSFET

Junction S/D MOSFET

Possible advantages • Better utilization of the metal/semiconductor interface Possible option to overcome the higher parasitic resistance • Modulation of the source barrier by the gate High Vg ⇒ barrier thin ⇒ tunneling current ⇑ ⇒ ION ⇑ Low Vg ⇒ barrier thick ⇒ tunneling current ⇓ ⇒ IOFF ⇓ • Better immunity from short channel effects Possible Disadvantage • Tradeoff between short channel effect vs. ION reduction due to the Schottky barrier Stanford University

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Schottky Barrier Source/Drain SOI MOSFET Lg~20 nm FETs with Complementary Silicides PtSi PMOS, ErSi NMOS

Gate Silicide

Si

Source ErSi2

BOX

Tilted Lg + Spacers =27nm Gate N+poly, ErSi2 W=25nm

PtSi PMOS 20 nm 4 nm 1.2 V 270 uA/um 100 mV/dec 5E5 -0.7 V

ErSi NMOS 15 nm 4 nm 1.2 V 190 uA/um 150 mV/dec 1E4 -0.1 V

1E-3

1E-5

• Metal S/D reduce extrinsic resistance • But Schottky barrier reduces Ion • Need low barrier technology to ensure high Ion

1E-6 1E-7 1E-8 1E-9 1E-10

J. Boker et al.- UC Berkeley Stanford University

|V sd| from 0.2V to 1.4V in steps of 0.4V

1E-4

|I d| (A/ µm)

Lg Tox Vg-Vt Ion Swing Ion/Ioff Vt

29

PMOS

NMOS T ox = 4nm L g = 15nm

T ox = 4nm L g = 20nm -1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Vg (V)


Doped vs. Schottky S/D DG Device Comparison Simulations

ION vs. IOFF

CV/I Delay

Source: King/Bokor,U.C. Berkeley  

Ref: R. Shenoy, PhD Thesis, Stanford 2004

Low barrier height metal contact required to achieve high ION and low CV/I delay Extensive research needed to develop a low barrier technology

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Outline •Junction/contact scaling issues •Shallow junction technology •Ohmic contacts Need to understand the physics of contacts resistance and develop technology to minmize it •Technology to form contacts

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Conduction Mechanisms for Metal/Semiconductor Contacts I φB

Low doping Ef

V Schottky

(a) Thermionic emission Medium doping

(b) Thermionic-field emission

Heavy doping

Ohmic

(c) Field emission.!

Contact resistance strongly depends on barrier height (φB) and doping density Stanford University

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Specific Contact Resistivity (ρc) V = Vbulk + 2Vcontact = I (Rbulk + 2Rcontact) n+

Rbulk =

dVbulk !l = dI A

!V !V

For a uniform current density

Rcontact =

dVcontact !c = dI A

• Specific contact resistivity and not contact resistance is the fundamental parameter characterizing a contact

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Tunneling - Ohmic Contacts Fm

Jsm

Xd =

Fs

2 K !o "i q Nd

When Xd ≤ 2.5 – 5 nm, electrons can “tunnel” through the barrier. Required doping is:

N d min "

2 K #o $i " 6.2 %10 1 9 cm &3 q X d2

J sm =

A*T F P( E)(1" Fm )dE k ! s

Net semiconductor to metal current is

# 2! B $ h

P(E) is the tunneling probability given by P(E) ~ exp% -

for X d = 2.5 nm

" sm * & ( N '

[

*

Current can be shown to be

J s m " exp #2xd 2m (q$ B # qV ) /h

Specific contact resistivity is of the form

% *( 2# $ m "c = " co exp'' B s ** h N & )

2

]

ohm + cm 2

ρc primarily depends upon • the metal-semiconductor work function, φΒ, • doping density, N, in the semiconductor and • the effective mass of the carrier, m*. Stanford University

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Specific Contact Resistivity to P-type Si P-type Si

$ 2" !c = ! co exp && B % qh

#sm* ' ) N )(

ohm * cm 2

Specific contact resistivity, ρc ↓ • As doping density N↑ • Barrier height φB ↓

Specific contact resistivity (Ωcm2)

Specific contact resistivity

NA (cm-3)

(S. Swirhun, PhD Thesis, Stanford Univ. 1987)

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Specific contact resistivity (Ωcm2)

Specific Contact Resistivity to N-type Dopants

• Similar trends for N-type Si • For a given doping density contact resistance is higher for n-type Si than p-type. • This can be attributed to the barrier height • φBn > φBp

(S. Swirhun, PhD Thesis, Stanford Univ. 1987)

ND (cm-3) Stanford University

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Solid Solubility of Dopants in Silicon

• Problem is worse for p-type dopants (B), solid solubility is lower • Maximum concentration of dopants is limited by solid solubility PROBLEM: Solid solubility of dopants does not scale ! Stanford University

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Barrier Height of Metals and Silicides to Si Ideal Schottky model

Barrier height to n- and p-type Si (φ BN hollow symbols and φ BP solid symbols)

Φm < χ

Φm > χ

Practical barrier with Fermi level pinning

. (Ref: S. Swirhun, PhD Thesis, Stanford Univ. 1987)

φBN ⇒ 2Eg/3 φBP ⇒ Eg/3

φBN + φBP = Eg Stanford University

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S/D Series Resistance [Ωµm]

Strategy for Series Resistance Scaling 300

Graded Junction Midgap Silicide

LG = 53 nm

240

Box Profile 180 Midgap Silicide Box Profile 120 Low-Barrier Silicide (ΦB = 0.2 eV) 60

Rov Rext Rdp Rcsd

0

Source/Drain Engineering Source: Jason Woo, UCLA

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Potential Solutions for S/D Engineering y=0

•

Rdp & Rcsd Scaling (ρc ↓) ⇒ Maximize Nif ( Rsh,dp ↓):

Sidewall

- Laser annealing - Elevated S/D ⇒ Minimize ΦB: - Dual low-barrier silicide (ErSi (PtSi2) for N(P)MOS)

Gate

Silicide

Rcsd

Rdp

• Rov & Rext Scaling

Rext

Rov

Nov(y)

x

Next(x)

⇒ Dopant Profile Control: ultra-shallow highly-doped box-shaped SDE profile (e.g., laser annealing, PAI + Laser Annealing)

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Bandgap Engineering

From M. C. Ozturk et al. (NCSU), IEDM2002

•

Si1-xGex S/D & germanosilicide contact − Assuming metal Fermi level is pinned near midgap − Similar barrier heights on n- or p-type material − Smaller bandgap for Si1-xGex − Reduction of Rcsd with single contact metal

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Energy band diagram and charging character of interface states for the metal-dielectric interface  Ideal Schottky model: when a metal and a semiconductor or a dielectric form an interface, there is no charge transfer across the interface  A semiconductor or dielectric surface has gap states due to the broken surface bonds. These are spread across the energy gap.  The wave functions of electrons in the metal tail or decay into the semiconductor in the energy range where the conduction band of the metal overlaps the semiconductor band gap. These resulting states in the forbidden gap are known as metal-induced gap states (MIGS) or simply intrinsic states.  The energy level in the band gap at which the dominant character of the interface states changes from donorlike to acceptorlike is called the charge neutrality level ECNL Stanford University

Yeo, King, and Hu, J. Appl. Phys., 15 Dec. 2002

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Fermi Level Pinning

Energy band structure of the Schottky contact and the electron energy dependence of the charging character of the metal semiconductor interface states.  The metal work function is pinned near the charge neutrality level.  The charge neutrality level is defined as the energy level at which the character of the interface states changes from donor-like to acceptor-like.  The charge neutrality level is situated at around one-third of the band gap in the case of silicon ⇒ φbn = 2Eg/3 and φbp = Eg/3

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Fermi-level de-pinning  Can we alter the charge neutrality level? It may be possible to do so by passivating the interface states. This can be done by modifying the interface. An issue of current research.  An example is selenium passivation of Si/Mg interface

the reconstructed Si [001] surface

Se-passivated Si [001] surface

Band diagram of Mg–Si contacts (a) without interface states and (b) with interface states. Stanford University

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I –V characteristics of Mg contacts to Si M. Tao et al., APL, 2003


Contact Resistance: 3D Model Contact

I

Majority carrier continuity equation outside the contact is

!" J =

I

#J x #J y #J z + + =0 #x #y #z

Current density in the semiconductor is

Metal

I

Silicon

Silicide

J = !"E = "#v

Combining these two equations we obtain ! " #!V = 0

Current I

Total current over the contact area is I tot = " $ J # dA

• Current flow in a contact is highly non-uniform • Contact resistance does not scale with area

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Solution of the above equations gives information about contact resistance. ! However, calculations are very involved.

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Transmission Line Contact Model A simplified 1D solution of the contacts is

# & x I(x) = I1 exp % ! ( " R $ c s'

=

I1 exp( ! x lt )

lt = !c Rs lt is the characteristic length of the transmission line - the distance at which 63% of the current has transferred into the metal.

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Measurement of Contact Resistance and Specific Contact Resistivity (ρc) R f = V f /I =

Rs" c coth( d /lt ) w

For a very large value of lt or for d << lt

Rf !

! Re = Ve /I =

"c wd

Rs" c w sinh( d /lt )

• Rf gives reasonable assessment of the source/drain contact resistance including the resistance of the semiconductor under the contact • Specific contact resistivity, ! ρc, can be calculated by measuring I, Vf or Ve • Measurement of Rf or Re is not straightforward and needs specialized test structures Stanford University

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Test Structure to Measure Contact Resistance: Transmission Line Tap Resistor

V24 = V f + IRSi + V f R

f V Rt = 24 = 2R f + Rs ls w I Rs ! c R f = V f / I1 = coth (d / lt ) is a very small number w

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Test Structure to Measure Contact Resistance: Cross-bridge Kelvin Structure

1

Metal

2

. l

l

l

l

N+ Diffusion

4

3

.

V V ! Rk = k = 14 = 2c I I23 l

Vk

.

Metal N+ Diffusion Contact

I

Cross-bridge Kelvin structure used to measure an average contact resistance, called RK in the figure

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Error in Specific Contact Resistivity due to 1-D Modeling 1-D model Specific contact resistivity (ρc)

2-D model Contact resistance

• Specific contact resistivity (ρc) is a fundamental property of the interface and should be independent of contact area • 1-D models overestimate the contact resistance (Rc) • 2-D models give more accurate results and should be used Stanford University

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Aluminum Contacts to Si Aluminum Oxide N+

Oxide

Silicon

• Silicon has high solubility in Al ~ 0.5% at 450ºC • Silicon has high diffusivity in Al • Si diffuses into Al. Voids form in Si which fill with Al: “Spiking” occurs.

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Al/Si Alloy Contacts to Si Al-Si phase diagram

By adding 1-2% Si in Al to satisfy solubility requirement junction spiking is minimmized

But Si precipitation can occur when cool down to room temperature ⇒ bad contacts to N+ Si Stanford University

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Silicide Contacts Barrier TiW TiN

Aluminum

Oxide N+ Contact

Oxide TiSi2 PtSi

Silicon

• Silicides like PtSi, TiSi2 make excellent contacts to Si • However, they react with Al • A barrier like TiN or TiW prevents this reaction

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Silicide Contacts

Similar methods are used for other silicides Stanford University

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Interfacial reactions

Integrity of ohmic contacts due to a physical barrier between Al and silicide Schottky barrier reduction due to Al reaction with PtSi ΦB (eV)

T (°C)

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Barriers Structure

Al/PtSi/Si

Failure Temperature (˚C) 350

Al/TiSi2/Si

400

Al/NiSi/Si

400

Al/CoSi2/Si

400

Al/Ti/PtSi/Si

450

Al/Ti30W70/PtSi/Si

500

Al/TiN/TiSi2/Si

550

Failure Mechanism (Reaction products) Compound formation (Al2Pt, Si) Diffusion (Al5Ti7Si12, Si at 550˚C) Compound formation (Al3Ni, Si) Compound formation Al9Co2, Si) Compound formation (Al3Ti) Diffusion (Al2Pt, Al12W at 500˚C) Compound formation (AlN, Al3Ti)

• Silicides react with Al at T < 400°C • A barrier like TiN or TiW prevents this reaction upto T > 500°C Stanford University

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Shallow Junctions Contacts - web.stanford.edu

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