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will take your exam. We are offering the FE exam on campus for a limited number of students. Details are as follows: • Saturday, October 26th. • Engineering Complex , Room. 109. • Testing begins at 8:00 am, but show up by 7:15 am! Dr. A . Pilhevari a
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The Finite Element Analysis (FEA) is a numerical methodfor solving problems of engineering and mathematical physics. Useful for problems with complicated
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Digital Logic Design Page 3 Contents Chapter 1. Number Systems, Number Representations, and Codes ..... 6
Pass-Transistor Logic
Topics
Transmission Gate
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Pass-transistor Logic Dynamic CMOS
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Pass-Transistor Logic •
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NMOS-Only Logic
Example: AND Gate
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Resistance of Transmission Gate
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Pass-Transistor Logic •
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5
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XOR
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1
Pass-Transistor Logic • • •
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Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
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In many cases, uses fewer transistors Can be difficult to design Usually requires complemented versions of all signals Difficult to layout Transmission gate looks like a RC line Delay analysis is not as well defined in terms of sizing choices
fan-in of n requires 2n transistors (n N-type and n P-type)
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
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requires only n+2 (n+1 N-type and 1 P-type) transistors (can be further reduced to n+1)
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Dynamic CMOS •
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Dynamic Gate
nMOS logic structure with pre-charged pullup
•Pre-charge to VDD when clock is low •Evaluate when clock is high
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Conditions on Output •
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Properties of Dynamic Gates
Once the output of a dynamic gate is discharged, it cannot be charged again until the next pre-charge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
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Logic function is implemented by the PDN only
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number of transistors is N + 2 (versus 2N for static complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD) Sizing of the devices does not affect the logic levels (ratioless)
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2
Properties of Dynamic Gates
Properties of Dynamic Gates
Faster switching speeds
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Properties of Dynamic Gates
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Advantages
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low noise margin (NML)
Needs a pre-charge/evaluate clock
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Fewer transistors than CMOS Smaller load capacitance - faster speed
Disadvantages
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no static current path exists between VDD and GND no glitching (static CMOS has many glitches) higher transition probabilities extra load on Clk
Dynamic CMOS
PDN starts to work as soon as the input signals exceed VTn,
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Overall power dissipation usually higher than static CMOS (mainly due to clock)
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reduced load capacitance due to smaller input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) Ideally, no Isc, so all the current provided by PDN goes into discharging CL
Leakage Charge sharing Cannot be cascaded directly Only 0→1 transitions allowed at inputs, thus cannot be connected to static gate directly
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Solution to Charge Leakage
Issues in Dynamic Design 1: Charge Leakage
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Increase size of inverter to increase capacitance
Dominant component is sub-threshold current
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3
Dynamic CMOS
Issues in Dynamic Design 2: Charge Sharing
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Charge Sharing • Assume that the internal capacitances
have been discharged • In the pre-charge phase, the output capacitance gets charged • During evaluation, if all the inputs are high except the bottom one, the output capacitance gets distributed to the internal capacitance Co • The output voltage will drop to VDD C + 2C o i • This could be low enough to trigger the inverter, causing a wrong value on the output
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
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Solution to Charge Sharing
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Dynamic CMOS Cascade problem
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Pre-charge internal nodes using a clock driven transistor (at the cost of increased area and power)
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Since the evaluation from the first stage takes some time, the second stage will start evaluating with the pre-charged internal value rather than the inputs 21
Cascading Dynamic Gates
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Domino Logic •
Solves cascade problem
Since the pre-charged output from the first stage is 0, it will never activate the pull-down network in the second stage until the first stage evaluation has completed.
Only 0 → 1 transitions allowed at inputs!
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23
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4
NP Domino (Zipper) CMOS
Since the second stage is build from p-logic, the precharged output from the first stage will not activate the inputs of the second stage
