1 A/0.6 A, DC-to-DC Switching Regulator with Independent Positive and Negative Outputs
ADP5070
Data Sheet FEATURES
TYPICAL APPLICATION CIRCUIT ADP5070 SS
INBK
RC1
L1
COMP1
VPOS
CC1
SW1
EN1
D1 RFT1
CVREG FB1
VREG
RFB1 VIN CIN1
PVIN1 PVIN2 PVINSYS
PGND
EN2
VREF
COUT1
CVREF RFB2
RC2
FB2
COMP2 CC2 SYNC/FREQ SLEW SEQ AGND
COUT2
RFT2
SW2 D2 L2
VNEG 12068-001
Wide input supply voltage range: 2.85 V to 15 V Generates well regulated, independently resistor programmable VPOS and VNEG outputs Boost regulator to generate VPOS output Adjustable positive output to 39 V Integrated 1.0 A main switch Optional single-ended primary-inductor converter (SEPIC) configuration for automatic step-up/step-down Inverting regulator to generate VNEG output Adjustable negative output to VIN − 39 V Integrated 0.6 A main switch True shutdown for both positive and negative outputs 1.2 MHz/2.4 MHz switching frequency with optional external frequency synchronization from 1.0 MHz to 2.6 MHz Resistor programmable soft start timer Slew rate control for lower system noise Individual precision enable and flexible start-up sequence control for symmetric start, VPOS first, or VNEG first Out-of-phase operation UVLO, OCP, OVP, and TSD protection 4 mm × 4 mm, 20-lead LFCSP and 20-lead TSSOP −40°C to +125°C junction temperature range Supported by the ADIsimPower tool set
Figure 1.
APPLICATIONS Bipolar amplifiers, ADCs, DACs and multiplexers Charge-coupled device (CCD) bias supply Optical module supply RF power amplifier (PA) bias
GENERAL DESCRIPTION The ADP5070 is a dual high performance dc-to-dc regulator that generates independently regulated positive and negative rails. The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch in both regulators enables generation of an adjustable positive output voltage up to +39 V and a negative output voltage down to −39 V below input voltage. The ADP5070 operates at a pin selected 1.2 MHz/2.4 MHz switching frequency. The ADP5070 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. Both regulators implement programmable slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI). Flexible start-up sequencing is provided with the options of manual enable, simultaneous mode, positive supply first, and negative supply first. Rev. B
The ADP5070 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. During shutdown, both regulators completely disconnect the loads from the input supply to provide a true shutdown. Other key safety features in the ADP5070 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5070 is available in a 20-lead LFCSP or in a 20-lead TSSOP and is rated for a −40°C to +125°C junction temperature range. Table 1. Family Models Model ADP5070 ADP5071
Boost Switch (A) 1.0 2.0
Inverter Switch (A) 0.6 1.2
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ADP5070* PRODUCT PAGE QUICK LINKS Last Content Update: 11/29/2017
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EVALUATION KITS
• Bias Generation and Level Setting Made Easy with Multiple Range, User Programmable Voltage Output D/A Converter
• ADP5070/ADP5071 Evaluation Board
DOCUMENTATION Application Notes • AN-1359: Low Noise, Dual-Supply Solution Using the ADP5070 for the Precision AD5761R Bipolar DAC in Single-Supply Systems
DESIGN RESOURCES • ADP5070 Material Declaration • PCN-PDN Information • Quality And Reliability • Symbols and Footprints
• AN-1366: Using the ADP5070/ADP5071 to Create Positive and Negative Voltage Rails when VOUT < VIN
DISCUSSIONS
• AN-1368: Ferrite Bead Demystified
View all ADP5070 EngineerZone Discussions.
Data Sheet • ADP5070: 1 A/0.6 A, DC-to-DC Switching Regulator with Independent Positive and Negative Outputs
SAMPLE AND BUY Visit the product page to see pricing options.
User Guides • UG-758: Evaluating the ADP5070CP/ADP5071CP LFCSP DC-to-DC Switching Regulators/Converters • UG-848: Evaluating the ADP5070RE/ADP5071RE TSSOP DC-to-DC Switching Regulators/Converters
TOOLS AND SIMULATIONS • ADIsimPower™ Voltage Regulator Design Tool
TECHNICAL SUPPORT Submit a technical question or find your regional support number.
DOCUMENT FEEDBACK Submit feedback for this data sheet.
• ADP507x Design Tool
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ADP5070
Data Sheet
TABLE OF CONTENTS Features .............................................................................................. 1
Soft Start ...................................................................................... 15
Applications ....................................................................................... 1
Slew Rate Control ....................................................................... 15
Typical Application Circuit ............................................................. 1
Current-Limit Protection ............................................................ 15
General Description ......................................................................... 1
Overvoltage Protection .............................................................. 15
Revision History ............................................................................... 2
Thermal Shutdown .................................................................... 15
Specifications..................................................................................... 3
Start-Up Sequence ...................................................................... 15
Absolute Maximum Ratings ............................................................ 5
Applications Information .............................................................. 17
Thermal Resistance ...................................................................... 5
ADIsimPower Design Tool ....................................................... 17
ESD Caution .................................................................................. 5
Component Selection ................................................................ 17
Pin Configurations and Function Descriptions ........................... 6
Loop Compensation .................................................................. 20
Typical Performance Characteristics ............................................. 8
Common Applications .............................................................. 22
Theory of Operation ...................................................................... 14
Super Low Noise With Optional LDOs................................... 24
PWM Mode ................................................................................. 14
SEPIC Step-Up/Step-Down Operation ................................... 25
PSM Mode ................................................................................... 14
Layout Considerations ............................................................... 26
Undervoltage Lockout (UVLO) ............................................... 14
Outline Dimensions ....................................................................... 27
Oscillator and Synchronization ................................................ 14
Ordering Guide .......................................................................... 27
Internal Regulators ..................................................................... 14 Precision Enabling ...................................................................... 15
REVISION HISTORY 7/2017—Rev. A to Rev. B Changes to Table 10 and Table 11 ................................................ 23 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 6/2015—Rev. 0 to Rev. A Added 20-Lead TSSOP ...................................................... Universal Changes to Table 3 and Table 4 ....................................................... 5 Added Figure 3, Renumbered Sequentially .................................. 6 Changes to Figure 29 Caption and Figure 32 Caption .............. 11 Changes to Figure 37 Caption to Figure 39 Caption ................. 13 Changes to Internal Regulators Section ...................................... 14 Change to Soft Start Section.......................................................... 15 Changes to Output Capacitors Section, Soft Start Resistor Section, and Diodes Section ......................................................................... 18 Changes to Figure 50 Caption....................................................... 26 Added Figure 51.............................................................................. 26 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 2/2015—Revision 0: Initial Version
Rev. B | Page 2 of 27
Data Sheet
ADP5070
SPECIFICATIONS PVIN1 = PVIN2 = PVINSYS = 2.85 V to 15 V, VPOS = 15 V, VNEG = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter INPUT SUPPLY VOLTAGE RANGE QUIESCENT CURRENT Operating Quiescent Current PVIN1, PVIN2, PVINSYS (Total) Shutdown Current UVLO System UVLO Threshold Rising Falling Hysteresis OSCILLATOR CIRCUIT Switching Frequency SYNC/FREQ Input Input Clock Range Input Clock Minimum On Pulse Width Input Clock Minimum Off Pulse Width Input Clock High Logic Input Clock Low Logic PRECISION ENABLING (EN1, EN2) High Level Threshold Low Level Threshold Shutdown Mode Pull-Down Resistance INTERNAL REGULATOR VREG Output Voltage BOOST REGULATOR Feedback Voltage Feedback Voltage Accuracy Feedback Bias Current Overvoltage Protection Threshold Load Regulation Line Regulation Error Amplifier (EA) Transconductance Power FET On Resistance Power FET Maximum Drain Source Voltage Input Disconnect Switch On Resistance Current-Limit Threshold Minimum On Time Minimum Off Time
Symbol VIN
Min 2.85
Typ
Max 15
Unit V
Test Conditions/Comments PVIN1, PVIN2, PVINSYS
IQ
3.5
4.0
mA
ISHDN
5
10
µA
No switching, EN1 = EN2 = high, PVIN1 = PVIN2 = PVINSYS = 5 V No switching, EN1 = EN2 = low, PVIN1 = PVIN2 = PVINSYS = 5 V
VUVLO_RISING VUVLO_FALLING VHYS_1
2.85
2.5
2.8 2.55 0.25
V V V
fSW
1.130 2.240
1.200 2.400
1.270 2.560
MHz MHz
fSYNC tSYNC_MIN_ON tSYNC_MIN_OFF VH (SYNC) VL (SYNC)
1.000 100 100
2.600
MHz ns ns V V
VTH_H VTH_L VTH_S
1.125 1.025 0.4
PVINSYS
1.3 0.4 1.15 1.05
1.175 1.075
V V V
REN
1.48
MΩ
VREG
4.25
V
VFB1
0.8 −0.5 −1.5
IFB1 VOV1 ∆VFB1/ILOAD1 ∆VFB1/VPVIN1 gM1 RDS (ON) BOOST VDS (MAX) BOOST RDS (ON) INBK ILIM (BOOST)
270
1.00
+0.5 +1.5 0.1 0.86 0.0003 0.002 300 175 39 210 1.10 50 25
Rev. B | Page 3 of 27
330
1.20
V % % µA V %/mA %/V µA/V mΩ V mΩ A ns ns
SYNC/FREQ = low SYNC/FREQ = high (connect to VREG)
Internal circuitry disabled to achieve ISHDN
TJ = 25°C TJ = −40°C to +125°C At FB1 pin ILOAD11 = 5 mA to 150 mA VPVIN1 = 2.85 V to 14.5 V, ILOAD11 = 15 mA
ADP5070 Parameter INVERTING REGULATOR Reference Voltage Reference Voltage Accuracy
Symbol
Feedback Bias Current Overvoltage Protection Threshold Load Regulation
IFB2 VOV2 ∆(VREF − VFB2)/ ILOAD2 ∆(VREF − VFB2)/ VPVIN2 gM2 RDS (ON) INVERTER VDS (MAX) INVERTER
Hiccup Time THERMAL SHUTDOWN Threshold Hysteresis
Typ
Unit
0.74 0.0004
V % % V % % µA V %/mA
0.003
%/V
+0.5 +1.5 0.8
−0.5 −1.5
ILIM (INVERTER)
Max
1.60 −0.5 −1.5
VREF − VFB2
EA Transconductance Power FET On Resistance Power FET Maximum Drain Source Voltage Current-Limit Threshold Minimum On Time Minimum Off Time SOFT START Soft Start Timer for Boost and Inverting Regulators
Min
VREF
Feedback Voltage Feedback Voltage Accuracy
Line Regulation
1
Data Sheet
+0.5 +1.5 0.1
270
300 350 39
330
µA/V mΩ V
600
660 60 50
720
mA ns ns
Test Conditions/Comments
TJ = 25°C TJ = −40°C to +125°C TJ = 25°C TJ = −40°C to +125°C At FB2 pin after soft start has completed ILOAD21 = 5 mA to 75 mA VPVIN2 = 2.85 V to 14.5 V, ILOAD21 = 15 mA
tSS
4
ms
SS = open
32 8 × tSS
ms ms
SS resistor = 50 kΩ to GND
tHICCUP TSHDN THYS
150 15
°C °C
ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).
Rev. B | Page 4 of 27
Data Sheet
ADP5070
ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE
Table 3. Parameter PVIN1, PVIN2, PVINSYS INBK SW1 SW2 PGND, AGND VREG EN1, EN2, FB1, FB2, SYNC/FREQ COMP1, COMP2, SLEW, SS, SEQ, VREF Operating Junction Temperature Range Storage Temperature Range Soldering Conditions
Rating −0.3 V to +18 V −0.3 V to PVIN1 + 0.3 V −0.3 V to +40 V PVIN2 − 40 V to PVIN2 + 0.3 V −0.3 V to +0.3 V −0.3 V to lower of PVINSYS + 0.3 V or +6 V −0.3 V to +6 V −0.3 V to VREG + 0.3 V
θJA and ΨJT are based on a 4-layer printed circuit board (PCB) (two signal and two power planes) with nine thermal vias connecting the exposed pad to the ground plane as recommended in the Layout Considerations section. θJC is measured at the top of the package and is independent of the PCB. The ΨJT value is more appropriate for calculating junction to case temperature in the application. Table 4. Thermal Resistance
−40°C to +125°C
Package Type 20-Lead LFCSP 20-Lead TSSOP
−65°C to +150°C JEDEC J-STD-020
ESD CAUTION
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Rev. B | Page 5 of 27
θJA 60.2 58.5
θJC 36.5 35.0
ΨJT 0.63 0.60
Unit °C/W °C/W
ADP5070
Data Sheet
ADP5070 TOP VIEW (Not to Scale)
15 14 13 12 11
PVIN1 VREG AGND VREF FB2
NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.
1
20 SW2
SW1
2
19 PVIN2 18 PVINSYS
INBK
3
SYNC/FREQ
4
SEQ
5
SLEW
6
15 AGND
FB1
7
14 VREF
COMP1
8
13 FB2
EN1
9
12 COMP2
SS 10
12068-002
1 2 3 4 5
COMP1 6 EN1 7 SS 8 EN2 9 COMP2 10
INBK SYNC/FREQ SEQ SLEW FB1
PGND
17 PVIN1
ADP5070 TOP VIEW
16 VREG
11 EN2
12068-050
20 19 18 17 16
SW1 PGND SW2 PVIN2 PVINSYS
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.
Figure 2. 20-Lead LFCSP Pin Configuration
Figure 3. 20-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions Pin No. LFCSP TSSOP 1 3 2 4
Mnemonic INBK SYNC/FREQ
3
5
SEQ
4
6
SLEW
5
7
FB1
6
8
COMP1
7
9
EN1
8
10
SS
9
11
EN2
10
12
COMP2
11
13
FB2
12
14
VREF
13 14 15 16 17
15 16 17 18 19
AGND VREG PVIN1 PVINSYS PVIN2
Description Input Disconnect Switch Output for the Boost Regulator. Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin high. To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching frequency, connect the SYNC/FREQ pin to an external clock. Start-Up Sequence Control. For manual VPOS/VNEG startup using an individual precision enabling pin, leave the SEQ pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to VREG (the EN1 pin can be used to enable the internal references early, if required). For a sequenced startup, pull the SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence; hold the other enable pin low. Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the fastest slew rate (best efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to VREG. For the slowest slew rate (best noise performance), connect the SLEW pin to AGND. Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost regulator output capacitor and AGND to program the output voltage. Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this pin and AGND. Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable the boost regulator output. Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start time, connect a resistor between the SS pin and AGND. Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable the inverting regulator output. Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin and AGND. Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the inverting regulator output capacitor and VREF to program the output voltage. Inverting Regulator Reference Output. Connect a 1.0 µF ceramic filter capacitor between the VREF pin and AGND. Analog Ground. Internal Regulator Output. Connect a 1.0 µF ceramic filter capacitor between the VREG pin and AGND. Power Input for the Boost Regulator. System Power Supply for the ADP5070. Power Input for the Inverting Regulator.
Rev. B | Page 6 of 27
Data Sheet Pin No. LFCSP TSSOP 18 20 19 1 20 2
ADP5070 Mnemonic SW2 PGND SW1 EPAD
Description Switching Node for the Inverting Regulator. Power Ground for the Boost and Inverting Regulators. Switching Node for the Boost Regulator. Exposed Pad. Connect the exposed pad to AGND.
Rev. B | Page 7 of 27
ADP5070
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS Typical performance characteristics are generated using the standard bill of materials for each input/output combination listed in Table 9, Table 10, and Table 11. 700
350
600
IOUT(MAX) (mA)
250
400 300
100
50
0
10
20
30
40
50
VPOS (V)
Figure 4. Boost Regulator Maximum Output Current, fSW = 1.2 MHz, TA = 25°C, Based on Target of 70% ILIM (BOOST)
0 –40
–20
–10
0
Figure 7. Inverting Regulator Maximum Output Current, fSW = 1.2 MHz, TA = 25°C, Based on Target of 70% ILIM (INVERTER) 350
250
IOUT(MAX) (mA)
500
300
400 300
150 100
100
50
10
20
30
40
50
VPOS (V)
0 –40
12068-004
Figure 5. Boost Regulator Maximum Output Current, fSW = 2.4 MHz, TA = 25°C, Based on Target of 70% ILIM (BOOST)
–20
–10
0
VNEG (V)
Figure 8. Inverting Regulator Maximum Output Current, fSW = 2.4 MHz, TA = 25°C, Based on Target of 70% ILIM (INVERTER) 100
80
80
EFFICIENCY (%)
100
60
40
20
60
40
20 VIN = 3.3V, 1.2MHz VIN = 3.3V, 2.4MHz 0.01
0.1
1
LOAD (A)
12068-005
0 0.001
–30
0 0.001
VIN = 3.3V, 1.2MHz VIN = 3.3V, 2.4MHz 0.01
0.1
1
LOAD (A)
Figure 9. Inverting Regulator Efficiency vs. Current Load, VIN = 3.3 V, VNEG = −5 V, TA = 25°C
Figure 6. Boost Regulator Efficiency vs. Current Load, VIN = 3.3 V, VPOS = 5 V, TA = 25°C
Rev. B | Page 8 of 27
12068-008
0
12V, L = 15µH 5V, L = 15µH 5V, L = 10µH 3.3V, L = 10µH 15V, L = 6.8µH 12V, L = 6.8µH 15V, L = 15µH 3.3V, L = 6.8µH
200
200
0
VIN = VIN = VIN = VIN = VIN = VIN = VIN = VIN =
12068-007
VIN = 12V, L = 10µH VIN = 3.3V, L = 6.8µH VIN = 5V, L = 10µH VIN = 3.3V, L = 3.3µH VIN = 5V, L = 3.3µH VIN = 15V, L = 10µH
600
IOUT(MAX) (mA)
–30
VNEG (V)
700
EFFICIENCY (%)
5V, L = 15µH 3.3V, L = 10µH 15V, L = 15µH 15V, L = 22µH 12V, L = 15µH 12V, L = 22µH 3.3V, L = 6.8µH 5V, L = 10µH
150 100
0
VIN = VIN = VIN = VIN = VIN = VIN = VIN = VIN =
200
200
12068-003
IOUT(MAX) (mA)
500
300
12068-006
VIN = 5V, L = 10µH VIN = 3.3V, L = 6.8µH VIN = 5V, L = 6.8µH VIN = 3.3V, L = 4.7µH VIN = 12V, L = 15µH VIN = 15V, L = 15µH
ADP5070 100
80
80
60
40
20
VIN = 3.3V, 1.2MHz VIN = 3.3V, 2.4MHz VIN = 5V, 1.2MHz VIN = 5V, 2.4MHz 0.01
0.1
1
LOAD (A)
80
EFFICIENCY (%)
80
60
40
0.01
0.1
1
LOAD (A)
Figure 11. Boost Regulator Efficiency vs. Current Load, VPOS = 15 V, TA = 25°C
40
0 0.001
VIN = 3.3V, 1.2MHz VIN = 3.3V, 2.4MHz VIN = 5V, 1.2MHz VIN = 5V, 2.4MHz 0.01
0.1
1
LOAD (A)
Figure 14. Inverting Regulator Efficiency vs. Current Load, VNEG = −15 V, TA = 25°C 100
80
80
EFFICIENCY (%)
100
60
40
60
40
20
20 VIN = 5V, 1.2MHz VIN = 5V, 2.4MHz 0.01
0.1
1
LOAD (A)
Figure 12. Boost Regulator Efficiency vs. Current Load, VPOS = 34 V, TA = 25°C
0 0.001
12068-011
0 0.001
1
60
20
VIN = 3.3V, 1.2MHz VIN = 3.3V, 2.4MHz VIN = 5V, 1.2MHz VIN = 5V, 2.4MHz 12068-010
EFFICIENCY (%)
100
0 0.001
0.1 LOAD (A)
100
20
0.01
Figure 13. Inverting Regulator Efficiency vs. Current Load, VNEG = −9 V, TA = 25°C
Figure 10. Boost Regulator Efficiency vs. Current Load, VPOS = 9 V, TA = 25°C
EFFICIENCY (%)
0 0.001
VIN = 3.3V, 1.2MHz VIN = 3.3V, 2.4MHz VIN = 5V, 1.2MHz VIN = 5V, 2.4MHz
VIN = 5V, 1.2MHz VIN = 5V, 2.4MHz 0.01 LOAD (A)
0.1
12068-014
0 0.001
40
12068-013
20
60
12068-012
EFFICIENCY (%)
100
12068-009
EFFICIENCY (%)
Data Sheet
Figure 15. Inverting Regulator Efficiency vs. Current Load, VNEG = −34 V, TA = 25°C
Rev. B | Page 9 of 27
Data Sheet
100
100
80
80
EFFICIENCY (%)
60
40
40
20 TA = +125°C TA = +25°C TA = –40°C 0.01
0.1
1
LOAD (A)
0 0.001
12068-015
0 0.001
0.01
0.1
1
LOAD (A)
Figure 16. Boost Regulator Efficiency over Temperature, VIN = 5 V, VPOS = 15 V, fSW = 1.2 MHz
Figure 19. Inverting Regulator Efficiency over Temperature, VIN = 5 V, VNEG = −15 V, fSW = 1.2 MHz 0.5
0.3
0.1
–0.1
–0.3 VOUT ACCURACY VFB1 ACCURACY 0
5
10
15
20
VIN (V)
0.1
–0.1
–0.3 VOUT ACCURACY VREF ACCURACY VFB2 ACCURACY
–0.5
12068-016
–0.5
0.3
0
5
10
15
12068-019
VARIATION FROM NOMINAL (%)
0.5
20
VIN (V)
Figure 17. Boost Regulator Line Regulation, VPOS = 15 V, fSW = 1.2 MHz, 15 mA Load, TA = 25°C
Figure 20. Inverting Regulator Line Regulation, VNEG = −15 V, fSW = 1.2 MHz, 15 mA Load, TA = 25°C
0.5 LOAD REGULATION, CHANGE IN VFB2 (%)
0.5
0.3
0.1
–0.1
–0.3 1.2MHz 2.4MHz –0.5 0
0.05
0.10
0.15
0.20
0.25
LOAD (A)
Figure 18. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V
0.3
0.1
–0.1
–0.3 1.2MHz 2.4MHz –0.5
12068-017
LOAD REGULATION, CHANGE IN VFB1 (%)
TA = +125°C TA = +25°C TA = –40°C 12068-018
20
VARIATION FROM NOMINAL (%)
60
0
0.05 LOAD (A)
0.10
12068-020
EFFICIENCY (%)
ADP5070
Figure 21. Inverting Regulator Load Regulation, VIN = 5 V, VNEG = −15 V
Rev. B | Page 10 of 27
Data Sheet
ADP5070 0.5
0.1
–0.1
–0.3
–0.5 0
0.06
0.04
0.02
0.08
0.12
0.10
INVERTING REGULATOR LOAD (A)
Figure 22. Cross Regulation, Boost Regulator VFB1 Regulation over Inverting Regulator Current Load, VIN = 5 V, VPOS = 15 V, VNEG = -15 V, fSW = 2.4 MHz, TA = 25°C, Boost Regulator Run in Continuous Conduction Mode with Fixed Load for Test
0.3
0.1
–0.1
–0.3
–0.5 0.05
0
0.10
0.20
0.15
0.25
BOOST REGULATOR LOAD (A)
12068-024
VFB2 DEVIATION FROM AVERAGE VALUE (%)
0.3
12068-021
VFB1 DEVIATION FROM AVERAGE VALUE (%)
0.5
Figure 25. Cross Regulation, Inverting Regulator VFB2 Regulation over Boost Regulator Current Load, VIN = 5 V, VPOS = 15 V, VNEG = −15 V, fSW = 2.4 MHz, TA = 25°C, Inverting Regulator Run in Continuous Conduction Mode with Fixed Load for Test 0.72
1.20 TA = +125°C TA = +25°C TA = –40°C
1.18
TA = +125°C TA = +25°C TA = –40°C
0.70
1.16
0.68
1.12
ILIMIT (A)
ILIMIT (A)
1.14
1.10
0.66
1.08
0.64 1.06 1.04
0.62
0
2
4
6
8
10
12
14
16
VIN (V)
0.60
12068-022
1.00
Figure 23. Boost Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN) over Temperature
0
4
6
8
10
12
14
16
VIN (V)
Figure 26. Inverting Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN) over Temperature 1.27
2.54
2.49
OSCILLATOR FREQUENCY (MHz)
TA = +125°C TA = +25°C TA = –40°C
2.44
2.39
2.34
2.29
TA = +125°C TA = +25°C TA = –40°C
1.25 1.23 1.21 1.19 1.17
2.24 0
2
4
6
8 VIN (V)
10
12
14
16
1.13
Figure 24. Oscillator Frequency vs. Input Voltage (VIN) over Temperature, SYNC/FREQ Pin = High
0
2
4
6
8 VIN (V)
10
12
14
16
12068-026
1.15
12068-023
OSCILLATOR FREQUENCY (MHz)
2
12068-025
1.02
Figure 27. Oscillator Frequency vs. Input Voltage (VIN) over Temperature, SYNC/FREQ Pin = Low
Rev. B | Page 11 of 27
ADP5070
Data Sheet 5.0
12
10
8 6
4
2
0 0
2
4
6
8
10
12
14
16
VIN (V)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 TA = +125°C TA = +25°C TA = –40°C
0.5 0
12068-027
TA = +125°C TA = +25°C TA = –40°C
4.5
0
2
4
6
8
10
12
14
16
VIN (V)
Figure 28. Shutdown Quiescent Current vs. Input Voltage (VIN) over Temperature, Both ENx Pins Below Shutdown Threshold
12068-030
OPERATING QUIESCENT CURRENT (mA)
Figure 31. Operating Quiescent Current vs. Input Voltage (VIN) over Temperature, Both ENx Pins On
T
T
VIN
VIN
VPOS
VNEG
2
2
1
1
VFB1
VFB2
3
B
CH1 1.0V BW CH2 100mV CH3 5.0mV BW
W
4.00ms T
CH1
5.00V
14.0ms
12068-028
3
CH1 1V BW
B
CH2 100mV
W
B
CH3 5mV
4.00ms T
W
CH1
5.0V
14.0ms
12068-031
SHUTDOWN QUIESCENT CURRENT (µA)
14
Figure 32. Inverting Regulator Line Transient, VIN = 4.5 V to 5.5 V Step, VNEG = −15 V, RLOAD2 = 300 Ω, fSW = 2.4 MHz, TA = 25°C
Figure 29. Boost Regulator Line Transient, VIN = 4.5 V to 5.5 V Step, VPOS = 15 V, RLOAD1 = 300 Ω, fSW = 2.4 MHz, TA = 25°C
T
T
ILOAD1 ILOAD2
1
VNEG
VPOS
2
2
1
VFB2 3
VFB1
CH3 25mV
B
W
B
W
4.00ms T
CH1
13.160ms
137mA
CH1 10mA
12068-029
CH2 50mV
CH1 20mA
CH3 5mV
Figure 30. Boost Regulator Load Transient, VIN = 5 V Step, VPOS = 15 V, ILOAD1 = 120 mA to 150 mA Step, fSW = 2.4 MHz, TA = 25°C
CH2 50mV B
W
B
W
4.00ms T
13.0ms
CH1
50mA
12068-032
3
Figure 33. Inverting Regulator Load Transient, VIN = 5 V Step, VNEG = −15 V, ILOAD2 = 35 mA to 45 mA Step, fSW = 2.4 MHz, TA = 25°C
Rev. B | Page 12 of 27
Data Sheet
ADP5070 T
T
IINDUCTOR IINDUCTOR 1
1
SW2
SW1 2
2
VNEG
VPOS 3
2.0µs
CH1
0.0A
T 34.6%
CH1 100mA BW CH2 5V Ω BW CH3 500mV BW
Figure 34. Boost Regulator Skip Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 4 mA, fSW = 2.4 MHz, TA = 25°C
CH1
2.0µs
0A
T 17.4%
12068-036
CH1 200mA BW CH2 2.5V Ω BW CH3 500mV BW
12068-033
3
Figure 37. Inverting Regulator Skip Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VNEG = −5 V, ILOAD2 = 1 mA, fSW = 2.4 MHz, TA = 25°C T
T
IINDUCTOR
IINDUCTOR 1
1
SW2
SW1
2
2
VNEG
VPOS
3
CH1
152mA
CH1 100mA BW CH2 5.0V Ω BW 100ns CH3 500mV BW T 17.4%
12068-034
CH1 200mA BW CH2 2.5V Ω BW 100ns CH3 500mV BW T 34.6%
Figure 35. Boost Regulator Discontinuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 35 mA, fSW = 2.4 MHz, TA = 25°C
CH1
80mA
12068-037
3
Figure 38. Inverting Regulator Discontinuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VNEG = −5 V, ILOAD2 = 6 mA, fSW = 2.4 MHz, TA = 25°C
T
T
IINDUCTOR 1
1
IINDUCTOR SW2
2
SW1 2
VNEG
3
VPOS
152mA
CH1 100mA BW CH2 5V Ω BW CH3 500mV BW
Figure 36. Boost Regulator Continuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 90 mA, fSW = 2.4 MHz, TA = 25°C
100ns T 17.4%s
CH1
172mA
12068-038
CH1
12068-035
CH1 200mA BW CH2 2.5V Ω BW 100ns CH3 500mV BW T 34.6%
3
Figure 39. Inverting Regulator Continuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V, VNEG = −5 V, ILOAD2 = 35 mA, fSW = 2.4 MHz, TA = 25°C
Rev. B | Page 13 of 27
ADP5070
Data Sheet
THEORY OF OPERATION VIN CVREG PVIN1
SYNC/FREQ
PVIN2
VREG
PVINSYS
CURRENT SENSE
INBK SWITCH CONTROL
HV REGULATOR
INVERTER PWM CONTROL
INBK
D2
SW2 L1 VOUT1
D1
EN1
SW1
SLEW
REF1
RC1
RFB2
INVERTER_ENABLE REF_1V6
+
THERMAL SHUTDOWN
1.5MΩ
COMP1
FB2
BOOST_ENABLE
SEQUENCE CONTROL
ERROR AMP
FB1 FB2
CC1 SLEW
EN1
COMP2
4µA OVP
EN2 SEQ
VREF CVREF
VREG
UVLO
RFT2
REF2
–
1.5MΩ
RFB1
–
ERROR AMP +
OSCILLATOR
CURRENT SENSE
FB1
COUT2
PLL
BOOST PWM CONTROL PGND
L2
EN2
COUT1 RFT1
SLEW
HV BAND GAP
START-UP TIMERS
REFERENCE GENERATOR
SS RSS (OPTIONAL)
REF1 REF2
RC2
REF_1V6 CC2 AGND
12068-039
CIN
Figure 40. Functional Block Diagram
PWM MODE The boost and inverting regulators in the ADP5070 operate at a fixed frequency set by an internal oscillator. At the start of each oscillator cycle, the MOSFET switch turns on, applying a positive voltage across the inductor. The inductor current (IINDUCTOR) increases until the current sense signal crosses the peak inductor current threshold that turns off the MOSFET switch; this threshold is set by the error amplifier output. During the MOSFET off time, the inductor current declines through the external diode until the next oscillator clock pulse starts a new cycle. It regulates the output voltage by adjusting the peak inductor current threshold.
PSM MODE During light load operation, the regulators can skip pulses to maintain output voltage regulation. Skipping pulses increases the device efficiency.
UNDERVOLTAGE LOCKOUT (UVLO) The undervoltage lockout circuitry monitors the PVINSYS pin voltage level. If the input voltage drops below the VUVLO_FALLING threshold, both regulators turn off. After the PVINSYS pin voltage rises above the VUVLO_RISING threshold, the soft start period initiates, and the regulators are enabled.
OSCILLATOR AND SYNCHRONIZATION The ADP5070 initiates the drive of the boost regulator SW1 pin and the inverting regulator SW2 pin 180° out of phase to reduce peak current consumption and noise.
A phase-locked loop (PLL)-based oscillator generates the internal clock and offers a choice of two internally generated frequency options or external clock synchronization. The switching frequency is configured using the SYNC/FREQ pin options shown in Table 6. For external synchronization, connect the SYNC/FREQ pin to a suitable clock source. The PLL locks to an input clock within the range specified by fSYNC. Table 6. SYNC/FREQ Pin Options SYNC/FREQ Pin High Low External Clock
Switching Frequency 2.4 MHz 1.2 MHz 1 × clock frequency
INTERNAL REGULATORS The internal VREG regulator in the ADP5070 provides a stable power supply for the internal circuitry. The VREG supply can be used to provide a logic high signal for device configuration pins but must not be used to supply external circuitry. The VREF regulator provides a reference voltage for the inverting regulator feedback network to ensure a positive feedback voltage on the FB2 pin. A current-limit circuit is included for both regulators to protect the circuit from accidental loading.
Rev. B | Page 14 of 27
Data Sheet
ADP5070
PRECISION ENABLING
CURRENT-LIMIT PROTECTION
The ADP5070 has an individual enable pin for the boost and inverting regulators: EN1 and EN2. The enable pins feature a precision enable circuit with an accurate reference voltage. This reference allows the ADP5070 to be sequenced easily from other supplies. It can also be used as a programmable UVLO input by using a resistor divider.
The boost and inverting regulators in the ADP5070 include current-limit protection circuitry to limit the amount of forward current through the MOSFET switch.
The enable pins have an internal pull-down resistor that defaults each regulator to off when the pin is floating. When the voltage at the enable pins is greater than the VTH_H reference level, the regulator is enabled.
When the peak inductor current exceeds the overcurrent limit threshold for a number of clock cycles during an overload or short-circuit condition, the regulator enters hiccup mode. The regulator stops switching and then restarts with a new soft start cycle after tHICCUP and repeats until the overcurrent condition is removed.
OVERVOLTAGE PROTECTION
SOFT START Each regulator in the ADP5070 includes soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. The soft start time is internally set to the fastest rate when the SS pin is open. Connecting a resistor between SS and AGND allows the adjustment of the soft start delay. The delay length is common to both regulators.
SLEW RATE CONTROL The ADP5070 employs programmable output driver slew rate control circuitry. This circuitry reduces the slew rate of the switching node as shown in Figure 41, resulting in reduced ringing and lower EMI. To program the slew rate, connect the SLEW pin to the VREG pin for normal mode, to the AGND pin for slow mode, or leave it open for fast mode. This configuration allows the use of an open-drain output from a noise sensitive device to switch the slew rate from fast to slow, for example, during analog-to-digital converter (ADC) sampling. Note that slew rate control causes a trade-off between efficiency and low EMI.
An overvoltage protection mechanism is present on the FB1 and FB2 pins for the boost and inverting regulators. On the boost regulator, when the voltage on the FB1 pin exceeds the VOV1 threshold, the switching on SW1 stops until the voltage falls below the threshold again. This functionality is permanently enabled on this regulator. On the inverting regulator, when the voltage on the FB2 pin drops below the VOV2 threshold, the switching stops until the voltage rises above the threshold. This functionality is enabled after the soft start period has elapsed.
THERMAL SHUTDOWN In the event that the ADP5070 junction temperature rises above TSHDN, the thermal shutdown circuit turns off the IC. Extreme junction temperatures can be the result of prolonged high current operation, poor circuit board design, and/or high ambient temperature. Hysteresis is included so that when thermal shutdown occurs, the ADP5070 does not return to operation until the onchip temperature drops below TSHDN minus THYS. When resuming from thermal shutdown, a soft start is performed on each enabled channel.
START-UP SEQUENCE The ADP5070 implements a flexible start-up sequence to meet different system requirements. Three different enabling modes can be implemented via the SEQ pin, as explained in Table 7.
FASTEST
Table 7. SEQ Pin Settings
12068-040
SLOWEST
Figure 41. Switching Node at Various Slew Rate Settings
SEQ Pin Open VREG Low
Description Manual enable mode Simultaneous enable mode Sequential enable mode
To configure the manual enable mode, leave the SEQ pin open. The boost and inverting regulators are controlled separately from their respective precision enable pins.
Rev. B | Page 15 of 27
ADP5070
Data Sheet
To configure the simultaneous enable mode, connect the SEQ pin to the VREG pin. Both regulators power up simultaneously when the EN2 pin is taken high. The EN1 pin enable can be used to enable the internal references ahead of enabling the outputs, if desired. The simultaneous enable mode timing is shown in Figure 42.
VPOS
VIN DISCONNECT SWITCH TURN ON
VPOS
TIME
VNEG 1. VPOS FOLLOWED BY VNEG (SEQ = LOW, EN1 = HIGH, EN2 = LOW)
VIN DISCONNECT SWITCH TURN ON
VPOS TIME
VIN DISCONNECT SWITCH TURN ON
SIMULTANEOUS ENABLE MODE (SEQ = HIGH, EN2 = HIGH)
12068-041
VNEG
TIME
Figure 42. Simultaneous Enable Mode
Rev. B | Page 16 of 27
VNEG 2. VNEG FOLLOWED BY VPOS (SEQ = LOW, EN2 = HIGH, EN1 = LOW) SEQUENTIAL ENABLE MODE
Figure 43. Sequential Enable Mode
12068-042
To configure the sequential enable mode, pull the SEQ pin low. In this mode, either VPOS or VNEG can be enabled first by using the respective EN1 pin or EN2 pin. Keep the other pin low. The secondary supply is enabled when the primary supply completes soft start and its feedback voltage reaches approximately 85% of the target value. The sequential enable mode timing is shown in Figure 43.
Data Sheet
ADP5070
APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL
Set the positive output for the boost regulator by
The ADP5070 is supported by the ADIsimPower design toolset. ADIsimPower is a collection of tools that produce complete power designs optimized to a specific design goal. These tools allow the user to generate a full schematic, bill of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and parts count while taking into consideration the operating conditions and limitations of the IC and all real external components. The ADIsimPower tool can be found at www.analog.com/adisimpower, and the user can request an unpopulated board through the tool.
RFT1 VPOS = VFB1 × 1 + R FB1 where: VPOS is the positive output voltage. VFB1 is the FB1 reference voltage. RFT1 is the feedback resistor from VPOS to FB1. RFB1 is the feedback resistor from FB1 to AGND. Set the negative output for the inverting regulator by
COMPONENT SELECTION
VNEG = VFB2 −
Feedback Resistors The ADP5070 provides an adjustable output voltage for both boost and inverting regulators. An external resistor divider sets the output voltage where the divider output must equal the appropriate feedback reference voltage, VFB1 or VFB2. To limit the output voltage accuracy degradation due to feedback bias current, ensure that the current through the divider is at least 10 times IFB1 or IFB2.
RFT2 (VREF − VFB2 ) RFB2
where: VNEG is the negative output voltage. VFB2 is the FB2 reference voltage. RFT2 is the feedback resistor from VNEG to FB2. RFB2 is the feedback resistor from FB2 to VREF. VREF is the VREF pin reference voltage.
Table 8. Recommended Feedback Resistor Values Desired Output Voltage (V) ±1.8 ±3 ±3.3 ±4.2 ±5 ±9 ±12 ±13 ±15 ±18 ±20 ±24 ±30 ±35
RFT1 (MΩ) 0.143 0.316 0.357 0.432 0.604 1.24 1.4 2.1 2.43 2.15 2.55 3.09 3.65 5.9
Boost/SEPIC Regulator Calculated RFB1 (kΩ) Output Voltage (V) 115 1.795 115 2.998 115 3.283 102 4.188 115 5.002 121 8.998 100 12.000 137 13.063 137 14.990 100 18.000 107 19.865 107 23.903 100 30.000 137 35.253
Rev. B | Page 17 of 27
RFT2 (MΩ) 0.332 0.475 0.523 0.715 1.15 1.62 1.15 2.8 2.32 2.67 2.94 3.16 4.12 5.11
Inverting Regulator Calculated RFB2 (kΩ) Output Voltage (V) 102 −1.804 100 −3.000 102 −3.302 115 −4.174 158 −5.023 133 −8.944 71.5 −12.067 162 −13.027 118 −14.929 113 −18.103 113 −20.014 102 −23.984 107 −30.004 115 −34.748
ADP5070
Data Sheet
Output Capacitors
VREG Capacitor
Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to the output voltage dc bias.
A 1.0 µF ceramic capacitor (CVREG) is required between the VREG pin and AGND.
Calculate the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage using the following equation: CEFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) × (1 − Tolerance)
A 1.0 µF ceramic capacitor (CVREF) is required between the VREF pin and AGND.
Soft Start Resistor A resistor can be connected between the SS pin and the AGND pin to increase the soft start time. The soft start time can be set by the resistor between 4 ms (268 kΩ) and 32 ms (50 kΩ). Leaving the SS pin open selects the fastest time of 4 ms. Figure 44 shows the behavior of this operation. Calculate the soft start time using the following formula: tSS = 38.4 × 10−3 − 1.28 × 10−7 × RSS (Ω) where 50 kΩ ≤ RSS ≤ 268 kΩ. SOFT START TIMER
32ms
where: CEFFECTIVE is the effective capacitance at the operating voltage. CNOMINAL is the nominal data sheet capacitance. TEMPCO is the worst-case capacitor temperature coefficient. DCBIASCO is the dc bias derating at the output voltage. Tolerance is the worst-case component tolerance. To guarantee the performance of the device, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Capacitors with lower effective series resistance (ESR) and effective series inductance (ESL) are preferred to minimize output voltage ripple. Note that the use of large output capacitors can require a slower soft start to prevent current limit during startup. A 10 µF capacitor is suggested as a good balance between performance and size.
Input Capacitor Higher value input capacitors help to reduce the input voltage ripple and improve transient response. To minimize supply noise, place the input capacitor as close as possible to the PVINSYS pin, PVIN1 pin, and PVIN2 pin. A low ESR capacitor is recommended. The effective capacitance needed for stability is a minimum of 10 µF. If the power pins are individually decoupled, it is recommended to use an effective minimum of a 5.6 µF capacitor on the PVIN1 and PVIN2 pins and a 3.3 µF capacitor on the PVINSYS pin. The minimum values specified exclude dc bias, temperature, and tolerance effects that are application dependent and must be taken into consideration.
4ms
SS PIN OPEN R2
R1
SOFT START RESISTOR
12068-043
Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 25 V or 50 V (depending on output) are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics.
VREF Capacitor
Figure 44. Soft Start Behavior
Diodes A Schottky diode with low junction capacitance is recommended for D1 and D2. At higher output voltages and especially at higher switching frequencies, the junction capacitance is a significant contributor to efficiency. Higher capacitance diodes also generate more switching noise. As a guide, a diode with less than 40 pF junction capacitance is preferred when the output voltage is above 5 V.
Inductor Selection for the Boost Regulator The inductor stores energy during the on time of the power switch, and transfers that energy to the output through the output rectifier during the off time. To balance the tradeoffs between small inductor current ripple and efficiency, inductance values in the range of 1 µH to 22 µH are recommended. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. However, lower inductance results in a higher peak current that can lead to reduced efficiency and greater input and/or output ripple and noise. A peakto-peak inductor ripple current close to 30% of the maximum dc input current for the application typically yields an optimal compromise.
Rev. B | Page 18 of 27
Data Sheet
ADP5070
For the inductor ripple current in continuous conduction mode (CCM) operation, the input (VIN) and output (VPOS) voltages determine the switch duty cycle (DUTY1) by
V − VIN + VDIODE1 DUTY1 = POS VPOS + VDIODE1 where VDIODE1 is the forward voltage drop of the Schottky diode (D1). The dc input current in CCM (IIN) can be determined by the following equation:
I IN =
I OUT1 (1 − DUTY1)
Using the duty cycle (DUTY1) and switching frequency (fSW), determine the on time (tON1) using the following equation:
t ON1 =
DUTY1 f SW
Inductor Selection for the Inverting Regulator The inductor stores energy during the on time of the power switch, and transfers that energy to the output through the output rectifier during the off time. To balance the tradeoffs between small inductor current ripple and efficiency, inductance values in the range of 1 µH to 22 µH are recommended. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. However, lower inductance results in a higher peak current that can lead to reduced efficiency and greater input and/or output ripple and noise. A peak-to-peak inductor ripple current close to 30% of the maximum dc current in the inductor typically yields an optimal compromise. For the inductor ripple current in continuous conduction mode (CCM) operation, the input (VIN) and output (VNEG) voltages determine the switch duty cycle (DUTY2) by
| VNEG | + VDIODE2 DUTY2 = V + | V | + VDIODE2 IN NEG
The inductor ripple current (∆IL1) in steady state is calculated by
∆I L1 =
where VDIODE2 is the forward voltage drop of the Schottky diode (D2).
VIN × tON1 L1
The dc current in the inductor in CCM (IL2) can be determined by the following equation:
Solve for the inductance value (L1) using the following equation:
L1 =
VIN × tON1 ∆I L1
Assuming an inductor ripple current of 30% of the maximum dc input current results in
L1 =
I OUT2 (1 − DUTY2)
I L2 =
Using the duty cycle (DUTY2) and switching frequency (fSW), determine the on time (tON2) by the following equation:
VIN × t ON1 × (1 − DUTY1)
t ON2 =
0.3 × IOUT1
Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is below the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. When the ADP5070 boost regulator is operated in CCM at duty cycles greater than 50%, slope compensation is required to stabilize the current mode loop. This slope compensation is built in to the ADP5070. For stable current mode operation, ensure that the selected inductance is equal to or greater than the minimum calculated inductance, LMIN1, for the application parameters in the following equation:
0.27 − 0.33 (µH) L1 > L MIN1 = VIN × (1 − DUTY1) Table 10 suggests a series of inductors to use with the ADP5070 boost regulator.
DUTY2 f SW
The inductor ripple current (∆IL2) in steady state is calculated by
∆I L2 =
VIN × t ON2 L2
Solve for the inductance value (L2) by the following equation:
L2 =
VIN × tON2 ∆I L2
Assuming an inductor ripple current of 30% of the maximum dc current in the inductor results in
L2 =
VIN × t ON2 × (1 − DUTY2) 0.3 × IOUT2
Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is below the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator.
Rev. B | Page 19 of 27
ADP5070
Data Sheet
When the ADP5070 inverting regulator is operated in CCM at duty cycles greater than 50%, slope compensation is required to stabilize the current mode loop. For stable current mode operation, ensure that the selected inductance is equal to or greater than the minimum calculated inductance, LMIN2, for the application parameters in the following equation:
0.27 L2 > L MIN2 = VIN × − 0.33 (µH) (1 − DUTY2) Table 11 suggests a series of inductors to use with the ADP5070 inverting regulator.
LOOP COMPENSATION The ADP5070 uses external components to compensate the regulator loop, allowing the optimization of the loop dynamics for a given application. It is recommended to use the ADIsimPower tool to calculate compensation components.
ZCOMP1 is the impedance of the series RC network from COMP1 to AGND. GCS1 is the current sense transconductance gain (the inductor current divided by the voltage at COMP1), which is internally set by the ADP5070 and is 6.25 A/V. ZOUT1 is the impedance of the load in parallel with the output capacitor. To determine the crossover frequency (fC1), it is important to note that, at that frequency, the compensation impedance (ZCOMP1) is dominated by a resistor (RC1), and the output impedance (ZOUT1) is dominated by the impedance of an output capacitor (COUT1). Therefore, when solving for the crossover frequency, the equation (by definition of the crossover frequency) is simplified to
AVL1 =
1 2π × f C1 × COUT1
Boost Regulator The boost converter produces an undesirable right half plane zero in the regulation feedback loop. This feedback loop requires compensating the regulator such that the crossover frequency occurs well below the frequency of the right half plane zero. The right half plane zero is determined by the following equation:
RLOAD1 (1 − DUTY1)2 2π × L1
where fC1 is the crossover frequency. To solve for RC1, use the following equation: RC1 =
2π × f C1 × COUT1 × (VPOS ) 2 VFB1 × VIN × GM1 × GCS1
where GCS1 = 6.25 A/V. Using typical values for VFB1 and GM1 results in
where: fZ1(RHP) is the right half plane zero frequency. RLOAD1 is the equivalent load resistance or the output voltage divided by the load current.
RC1 =
4188 × f C1 × COUT1 × (VPOS )2 VIN
For better accuracy, it is recommended to use the value of output capacitance, COUT1, expected for the dc bias conditions under which it operates under in the calculation for RC1.
V − VIN + VDIODE1 DUTY1 = POS VPOS + VDIODE1 where VDIODE1 is the forward voltage drop of the Schottky diode (D1). To stabilize the regulator, ensure that the regulator crossover frequency is less than or equal to one-tenth of the right half plane zero frequency.
After the compensation resistor is known, set the zero formed by the compensation capacitor and resistor to one-fourth of the crossover frequency, or
CC1 =
2 π × f C1 × RC1
where CC1 is the compensation capacitor value.
The boost regulator loop gain is
AVL1 =
=1
FB1
V VFB1 × IN × G M1 × ROUT1|| Z COMP1 × VPOS VPOS
ERROR AMPLIFIER COMP1 gM1
REF1
GCS1 × Z OUT1
RC1
CB1
CC1
where: AVL1 is the loop gain. VFB1 is the feedback regulation voltage VPOS is the regulated positive output voltage. VIN is the input voltage. GM1 is the error amplifier transconductance gain. ROUT1 is the output impedance of the error amplifier and is 33 MΩ.
12068-044
f Z1 (RHP ) =
VFB1 VIN × × GM1 × RC1 × GCS1 × VPOS VPOS
Figure 45. Compensation Components
The capacitor, CB1, is chosen to cancel the zero introduced by the output capacitor ESR. Solve for CB1 as follows:
Rev. B | Page 20 of 27
CB1 =
ESR × COUT1 RC1
Data Sheet
ADP5070
For low ESR output capacitance such as with a ceramic capacitor, CB1 is optional. For optimal transient performance, RC1 and CC1 may need to be adjusted by observing the load transient response of the ADP5070. For most applications, RC1 must be within the range of 1 kΩ to 200 kΩ, and CC1 must be within the range of 1 nF to 68 nF.
To determine the crossover frequency, it is important to note that, at that frequency, the compensation impedance (ZCOMP2) is dominated by a resistor, RC2, and the output impedance (ZOUT2) is dominated by the impedance of the output capacitor, COUT2. Therefore, when solving for the crossover frequency, the equation (by definition of the crossover frequency) is simplified to
VIN VFB2 × × G M2 × |VNEG| (VIN + 2 × | VNEG|) 1 RC2 × GCS 2 × =1 2π × f C2 × COUT2
Inverting Regulator The inverting converter, like the boost converter, produces an undesirable right half plane zero in the regulation feedback loop. This feedback loop requires compensating the regulator such that the crossover frequency occurs well below the frequency of the right half plane zero. The right half plane zero frequency is determined by the following equation: f Z2(RHP) =
where fC2 is the crossover frequency. To solve for RC2, use the following equation:
RLOAD2( 1 − DUTY2) 2π × L2 × DUTY2
2
RC2 =
where: fZ2(RHP) is the right half plane zero frequency. RLOAD2 is the equivalent load resistance or the output voltage divided by the load current.
2π × f C2 × COUT2 × |VNEG| × (VIN + (2 × | VNEG|) VFB2 × VIN × G M2 × GCS2
where GCS2 = 6.25 A/V. Using typical values for VFB2 and GM2 results in
RC2 =
|VNEG| + VDIODE2 DUTY2 = V + |V | + VDIODE2 NEG IN where VDIODE2 is the forward voltage drop of the Schottky diode (D2). To stabilize the regulator, ensure that the regulator crossover frequency is less than or equal to one-tenth of the right half plane zero frequency. The regulator loop gain is
AVL2
AVL2 =
4188 × f C2 × COUT 2 × | VNEG| × (VIN + (2 × | VNEG|) VIN
For better accuracy, it is recommended to use the value of output capacitance, COUT2, expected under the dc bias conditions that it operates under in the calculation for RC2. After the compensation resistor is known, set the zero formed by the CC2 and RC2 to one-fourth of the crossover frequency, or
CC2 =
2 π × f C2 × RC2
where CC2 is the compensation capacitor.
V VIN = FB2 × × GM2 × |VNEG| (VIN + 2 × | VNEG|)
FB2
ERROR AMPLIFIER COMP2 gM2
where: AVL2 is the loop gain. VFB2 is the feedback regulation voltage. VNEG is the regulated negative output voltage. VIN is the input voltage. GM2 is the error amplifier transconductance gain. ROUT2 is the output impedance of the error amplifier and is 33 MΩ. ZCOMP2 is the impedance of the series RC network from COMP2 to AGND. GCS2 is the current sense transconductance gain (the inductor current divided by the voltage at COMP2), which is internally set by the ADP5070 and is 6.25 A/V. ZOUT2 is the impedance of the load in parallel with the output capacitor.
RC2
CB2
CC2
12068-045
REF2
ROUT2|| Z COMP2 × GCS2 × ZOUT2
Figure 46. Compensation Component
The capacitor, CB2, is chosen to cancel the zero introduced by output capacitance, ESR. Solve for CB2 as follows:
CB2 =
ESR × C OUT2 RC2
For low ESR output capacitance, such as with a ceramic capacitor, CB2 is optional. For optimal transient performance, RC2 and CC2 may need to be adjusted by observing the load transient response of the ADP5070. For most applications, RC2 must be within the range of 1 kΩ to 200 kΩ, and CC2 must be within the range of 1 nF to 68 nF.
Rev. B | Page 21 of 27
ADP5070
Data Sheet
COMMON APPLICATIONS
Figure 47 shows the schematic referenced by Table 9 through Table 11 with example component values for +5 V to ±15 V generation. Table 9 shows the components common to all of the VIN and VOUT conditions.
Table 9 through Table 11 list a number of common component selections for typical VIN and VOUT conditions. These have been bench tested and provide an off the shelf solution. Note that when pairing a boost and inverting regulator bill of materials, choose the same VIN and switching frequency. To optimize components for an application, it is recommend to use the ADIsimPower toolset.
Table 9. Recommended Common Components Selections REF CIN1 CVREG CVREF
Value 10 µF 1 µF 1 µF
Part Number TMK316B7106KL-TD GRM188R71A105KA61D GRM188R71A105KA61D
ADP5070 SS
INBK
CC1 47nF
VREG VIN +5V
CIN1 10µF
RC2 15kΩ CC2 68nF
VPOS +15V
SW1
EN1
CVREG 1µF
L1 6.8µH D1 DFLS240
COMP1
FB1
RFT1 2.43MΩ RFB1 137kΩ
PVIN1 PVIN2 PVINSYS
PGND
EN2
VREF
CVREF 1µF RFB2 118kΩ
COMP2 SYNC/FREQ SLEW SEQ AGND
FB2
COUT2 10µF
RFT2 2.32MΩ
SW2 D2 DFLS240 L2 15µH
Figure 47. Typical +5 V to ±15 V Application
Rev. B | Page 22 of 27
COUT1 10µF
VNEG –15V
12068-046
RC1 12kΩ
Manufacturer Taiyo Yuden Murata Murata
Data Sheet
ADP5070
Table 10. Recommended Boost Regulator Components VIN (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 5 5 12 12
VPOS (V) 5 5 9 9 15 15 24 24 34 34 9 9 15 15 24 24 34 34 24 24
Freq. (MHz) 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4
L1 (µH) 3.3 2.2 4.7 2.2 6.8 4.7 6.8 6.8 6.8 10 4.7 3.3 6.8 3.3 10 4.7 10 10 15 6.8
L1 Manufacturer Part Number Wurth Coilcraft® Elektronik XAL4030-332ME_ XAL4020-222ME_ 74438356022 XAL4030-472ME_ 74438357047 XAL4020-222ME_ 74438356022 XAL4030-682ME_ 74438357068 XAL4030-472ME_ 74438357047 XAL4030-682ME_ 74438357068 XAL4030-682ME_ 74438357068 XAL4030-682ME_ 74438357068 XAL4040-103ME_ XAL4030-472ME_ 74438357047 XAL4030-332ME_ XAL4030-682ME_ 74438357068 XAL4030-332ME_ XAL4040-103ME_ XAL4030-472ME_ 74438357047 XAL4040-103ME_ XAL4040-103ME_ XAL4040-153ME_ XAL4030-682ME_ 74438357068
COUT1 (µF) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
COUT1, Murata Part GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L
D1, Diodes, Inc. Part DFLS240L DFLS240L DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240
RFT1 (MΩ) 0.604 0.604 1.24 1.24 2.43 2.43 3.09 3.09 4.22 4.22 1.24 1.24 2.43 2.43 3.09 3.09 4.22 4.22 3.09 3.09
RFB1 (kΩ) 115 115 121 121 137 137 107 107 102 102 121 121 137 137 107 107 102 102 107 107
CC1 (nF) 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47
RC1 (kΩ) 4.7 4.7 6.8 6.8 22 25 33 33 27 27 3.3 3.9 12 15 18 18 18 18 12 12
CC2 (nF) 47 47 47 47 47 47 47 47 47 47 47 47 68 47 47 47 47 47 47 47
RC2 (kΩ) 4.7 6.8 8.2 8.2 12 18 22 33 47 47 8.2 8.2 15 22 22 22 39 39 10 10
Table 11. Recommended Inverting Regulator Components VIN (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 5 5 12 12
VNEG (V) −5 −5 −9 −9 −15 −15 −24 −24 −34 −34 −9 −9 −15 −15 −24 −24 −34 −34 −24 −24
Freq. (MHz) 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4
L2 (µH) 6.8 4.7 10 4.7 10 4.7 10 6.8 10 10 10 6.8 15 6.8 15 6.8 15 10 22 15
L2, Manufacturer Part Number Wurth Coilcraft Elektronik XAL4030-682ME_ 74438357068 XAL4030-472ME_ 74438357047 XAL4040-103ME_ XAL4030-472ME_ 74438357047 XAL4040-103ME_ XAL4030-472ME_ 74438357047 XAL4040-103ME_ XAL4030-682ME_ 74438357068 XAL4040-103ME_ XAL4040-103ME_ XAL4040-103ME_ XAL4030-682ME_ 74438357068 XAL4040-153ME_ XAL4030-682ME_ 74438357068 XAL4040-153ME_ XAL4030-682ME_ 74438357068 XAL4040-153ME_ XAL4040-103ME_ XAL5050-223ME_ XAL4040-153ME_
COUT2 (µF) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
COUT2, Murata Part GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L
Rev. B | Page 23 of 27
D2, Diodes, Inc. Part DFLS240L DFLS240L DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240 DFLS240
RFT2 (MΩ) 1.15 1.15 1.62 1.62 2.32 2.32 3.16 3.16 4.99 4.99 1.62 1.62 2.32 2.32 3.16 3.16 4.99 4.99 3.16 3.16
RFB2 (kΩ) 158 158 133 133 118 118 102 102 115 115 133 133 118 118 102 102 115 115 102 102
ADP5070
Data Sheet
SUPER LOW NOISE WITH OPTIONAL LDOS Low dropout regulators (LDOs) can be added to the ADP5070 output to provide super low noise supplies for high performance ADCs, digital-to-analog converters (DACs), and other precision applications. Table 12 shows recommended companion devices, and Figure 48 shows a typical application schematic for ±15 V generation from a +5 V supply. ADP5070 SS
INBK
D1 DFLS240
COMP1 CC1 47nF
FB1
VREG VIN +5V
CIN1 10µF
RC2 12kΩ CC2 47nF
RFT1 2.15MΩ RFB1 113kΩ
PVIN1 PVIN2 PVINSYS
PGND
EN2
VREF
VOUT ADJ (5V)
COUT1 10µF
SS
VPOS = +15V RFT3 20kΩ RFB3 10kΩ
CNR3 1µF RNR3 1kΩ
COUT3 2.2µF
GND CSS3 1nF
CVREF 1µF
FB2
SYNC/FREQ SLEW SEQ AGND
CIN3 1µF
VIN
EN
ADP7182 COUT2 10µF
RFB2 100kΩ COMP2
ADP7142
+16V
SW1
EN1
CVREG 1µF
L1 3.3µH
RFT2 2.1MΩ
SW2
EN
VOUT ADJ
–16V
D2 DFLS240
CIN4 2.2µF
VIN GND
VNEG = –15V RFT4 52.3kΩ RFB4 59kΩ
CNR4 47µF RNR4 5.9kΩ
COUT4 2.2µF
12068-047
RC1 5.6kΩ
L2 6.8µH
Figure 48. Super Low Noise ±15 V Generation with Post Regulation by the ADP7142 (+40 V, +200 mA, Low Noise LDO) and ADP7182 (−28 V, −200 mA, Low Noise LDO)
Table 12. Recommended LDOs for Super Low Noise Operation Parameter VIN Range Fixed VOUT Adjustable VOUT IOUT IQ at No Load ISHDN Typical Soft Start PGOOD Noise (Fixed), 10 Hz to 100 kHz PSRR (100 kHz) PSRR (1 MHz) Package
ADP7102 3.3 V to 20 V 1.5 V to 9 V 1.22 V to 19 V 300 mA 400 µA 40 µA No Yes 15 µV rms
ADP7104 3.3 V to 20 V 1.5 V to 9 V 1.22 V to 19 V 500 mA 400 µA 40 µA No Yes 15 µV rms
ADP7105 3.3 V to 20 V 1.8 V, 3.3 V, 5 V 1.22 V to 19 V 500 mA 400 µA 40 µA Yes Yes 15 µV rms
ADP7118 2.7 V to 20 V 1.2 V to 5 V 1.2 V to 19 V 200 mA 50 µA 2 µA Yes No 11 µV rms
ADP7142 2.7 V to 40 V 1.2 V to 5 V 1.2 V to 39 V 200 mA 50 µA 2 µA Yes No 11 µV rms
ADP7182 −2.7 V to −28 V −1.8 V to −5 V −1.22 V to−27 V −200 mA −33 µA −2 µA No No 18 µV rms
60 dB 40 dB 8-lead LFCSP, 8-lead SOIC
60 dB 40 dB 8-lead LFCSP, 8-lead SOIC
60 dB 40 dB 8-lead LFCSP, 8-lead SOIC
68 dB 50 dB 6-lead LFCSP, 8-lead SOIC, 5-lead TSOT
68 dB 50 dB 6-lead LFCSP, 8-lead SOIC, 5-lead TSOT
45 dB 45 dB 6-lead LFCSP, 8-lead LFCSP, 5-lead TSOT
Rev. B | Page 24 of 27
Data Sheet
ADP5070
SEPIC STEP-UP/STEP-DOWN OPERATION SEPIC operation allows the positive output channel to produce a voltage higher or lower than VIN. Both standalone and coupled inductors are supported for this application. SEPIC designs are supported in the ADIsimPower toolset.
ADP5070 SS
INBK
RC1
L1A
L1B
STANDALONE OR COUPLED-INDUCTOR
COMP1 +5V/400mA
CC1
SW1 CS1 RFT1
CVREG VREG 1µF VIN = +12V
CIN1 10µF
D1
FB1
COUT1
RFB1
PVIN1 PVIN2 PVINSYS
PGND
EN2
VREF
CVREF RFB2 1µF
RC2 COMP2
FB2
CC2 SYNC/FREQ SLEW SEQ AGND
COUT2
RFT2
SW2 D2
–5V/400mA
L2
Figure 49. SEPIC Application for +12 V in to ±5 V Output Generation
Rev. B | Page 25 of 27
12068-048
EN1
ADP5070
Data Sheet
LAYOUT CONSIDERATIONS
16mm
•
•
•
• •
•
•
12068-049
•
Keep the input bypass capacitor, CIN1, close to the PVIN1 pin, the PVIN2 pin, and the PVINSYS pin. Route each of these pins individually to the pad of this capacitor to minimize noise coupling between the power inputs rather than connecting the three pins at the device. A separate capacitor can be used on the PVINSYS pin for the best noise performance. Keep the high current paths as short as possible. These paths include the connections between CIN1, L1, L2, D1, D2, COUT1, COUT2, and PGND and their connections to the ADP5070. Keep AGND and PGND separate on the top layer of the board. This separation avoids pollution of AGND with switching noise. Do not connect PGND to the EPAD on the top layer of the layout. Connect both AGND and PGND to the board ground plane with vias. Ideally, connect PGND to the plane at a point between the input and output capacitors. Connect the EPAD on its own to this ground layer with vias and connect AGND as near to the pin as possible between the CVREF and CVREG capacitors. Keep high current traces as short and wide as possible to minimize parasitic series inductance, which causes spiking and electromagnetic interference (EMI). Avoid routing high impedance traces near any node connected to the SW1 and SW2 pins or near Inductors L1and L2 to prevent radiated switching noise injection. Place the feedback resistors as close to the FB1 and FB2 pins as possible to prevent high frequency switching noise injection. Place the top of the upper feedback resistors, RFT1 and RFT2, or route traces to them from as close as possible to the top of COUT1 and COUT2 for optimum output voltage sensing. Place the compensation components as close as possible to COMP1 and COMP2. Do not share vias to the ground plane with the feedback resistors to avoid coupling high frequency noise into the sensitive COMP1 and COMP2 pins. Place the CVREF and CVREG capacitors as close to the VREG and VREF pins as possible. Ensure that short traces are used between VREF and RFB2.
Figure 50. Suggested LFCSP Layout; Vias Connected to the PCB Ground Plane, Not to Scale
12068-051
•
20mm
Layout is important for all switching regulators but is particularly important for regulators with high switching frequencies. To achieve high efficiency, good regulation, good stability, and low noise, a well-designed PCB layout is required. Follow these guidelines when designing PCBs:
Figure 51. Suggested TSSOP Layout; Vias Connected to the PCB Ground Plane, Not to Scale
Rev. B | Page 26 of 27
Data Sheet
ADP5070
OUTLINE DIMENSIONS DETAIL A (JEDEC 95)
4.10 4.00 SQ 3.90
PIN 1 INDICATOR
0.30 0.25 0.18 16
0.50 BSC
PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A)
20 1
15
2.75 2.60 SQ 2.35
EXPOSED PAD 5
11
0.80 0.75 0.70
SIDE VIEW
PKG-005089
BOTTOM VIEW
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
SEATING PLANE
0.25 MIN
6
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-21-2017-B
0.50 0.40 0.30
TOP VIEW
10
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11.
Figure 52. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-20-8) Dimensions shown in millimeters 4.25 4.20 4.15
6.60 6.50 6.40
11
20
4.50 4.40 4.30
TOP VIEW 1
3.05 3.00 2.95
EXPOSED PAD (Pins Up)
6.40 BSC
10
BOTTOM VIEW
1.05 1.00 0.80
1.20 MAX
0.15 0.05
0.30 0.19
SEATING PLANE COPLANARITY 0.10
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
8° 0° 0.20 0.09
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-ACT
05-08-2006-A
0.65 BSC
Figure 53. 20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP] (RE-20-1) Dimensions shown in millimeters
ORDERING GUIDE Model1 ADP5070ACPZ ADP5070ACPZ-R7 ADP5070AREZ ADP5070AREZ-R7 ADP5070CP-EVALZ ADP5070RE-EVALZ 1
Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C
Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP] 20-Lead Lead Frame Chip Scale Package [LFCSP] 20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP] 20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP] Evaluation Board for the LFCSP Evaluation Board for the TSSOP_EP
Z = RoHS Compliant Part.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12068-0-7/17(B)
Rev. B | Page 27 of 27
Package Option CP-20-8 CP-20-8 RE-20-1 RE-20-1