Quad SPDT ±5 V, +12 V, +5 V, and +3.3 V

4.5 Ω RON, Triple/Quad SPDT ±5 V, +12 V, +5 V, and +3.3 V Switches ADG1633/ADG1634

Data Sheet

FUNCTIONAL BLOCK DIAGRAMS

4.5 Ω typical on resistance 1 Ω on-resistance flatness Up to 206 mA continuous current ±3.3 V to ±8 V dual-supply operation 3.3 V to 16 V single-supply operation No VL supply required 3 V logic-compatible inputs Rail-to-rail operation ADG1633 16-lead TSSOP and 16-lead, 3 mm × 3 mm LFCSP ADG1634 20-lead TSSOP and 20-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

ADG1633 S1A D1 S1B S3B D3 S2B

S3A

D2 S2A LOGIC

IN1 IN2 IN3 EN 08319-001

FEATURES

SWITCHES SHOWN FOR A 1 INPUT LOGIC.

Figure 1. ADG1633 TSSOP and LFCSP

Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements

ADG1634 S1A

S4A

D1

D4

S1B

S4B

IN1

IN4

IN2

IN3

S2B

S3B

D2

The ADG1633 and ADG1634 are monolithic industrial CMOS (iCMOS®) analog switches comprising three independently selectable single-pole, double-throw (SPDT) switches and four independently selectable SPDT switches, respectively. All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. An EN input on the ADG1633 (LFCSP and TSSOP packages) and ADG1634 (LFCSP package only) is used to enable or disable the devices. When disabled, all channels are switched off. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications, where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments.

D3

S2A

S3A

08319-002

GENERAL DESCRIPTION

SWITCHES SHOWN FOR A 1 INPUT LOGIC.

Figure 2. ADG1634 TSSOP

ADG1634 S4A

S1A

D4

D1

S4B

S1B

S3B

S2B

D3

D2

S3A

S2A

IN1 IN2 IN3 IN4 EN SWITCHES SHOWN FOR A 1 INPUT LOGIC.

08319-003

LOGIC

Figure 3. ADG1634 LFCSP

Rev. B

Document Feedback

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ADG1633/ADG1634

Data Sheet

TABLE OF CONTENTS Features .............................................................................................. 1

Continuous Current per Channel, S or D ..................................7

Applications ....................................................................................... 1

Absolute Maximum Ratings ............................................................8

General Description ......................................................................... 1

ESD Caution...................................................................................8

Functional Block Diagrams ............................................................. 1

Pin Configurations and Function Descriptions ............................9

Revision History ............................................................................... 2

Typical Performance Characteristics ........................................... 11

Specifications..................................................................................... 3

Test Circuits ..................................................................................... 14

±5 V Dual Supply ......................................................................... 3

Terminology .................................................................................... 16

12 V Single Supply ........................................................................ 4

Outline Dimensions ....................................................................... 17

5 V Single Supply .......................................................................... 5

Ordering Guide .......................................................................... 19

3.3 V Single Supply ....................................................................... 6

REVISION HISTORY 8/2016—Rev. A to Rev. B Changed CP-20-4 to CP-20-10 .................................... Throughout Changes to Figure 5 .......................................................................... 9 Changes to Figure 7 ........................................................................ 10 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 9/2014—Rev. 0 to Rev. A Changes to Figure 26, Figure 27, Figure 28 ................................. 14 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 19 7/2009—Revision 0: Initial Version

Rev. B | Page 2 of 19

Data Sheet

ADG1633/ADG1634

SPECIFICATIONS ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH

25°C

−40°C to +85°C

−40°C to +125°C VDD to VSS

4.5 5 0.12 0.25 1 1.3 ±0.01 ±0.1 ±0.02 ±0.15 ±0.02 ±0.15

7

8

0.3

0.35

1.7

2

±1.5

±12

±2

±20

±2

±20 2.0 0.8

±1 ±0.1

Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION

8

V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max nA typ µA max pF typ

Break-Before-Make Time Delay, tD

161 200 61 79 162 199 44

Charge Injection Off Isolation

−12.5 −64

ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ

Channel-to-Channel Crosstalk

−64

dB typ

Total Harmonic Distortion + Noise (THD + N)

0.3

% typ

103 19 33 57

MHz typ pF typ pF typ pF typ

tON (EN) tOFF (EN)

236

264

88

98

232

259 30

−3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD VDD/VSS 1

Unit

0.001 1.0 ±3.3/±8

Guaranteed by design, but not subject to production test. Rev. B | Page 3 of 19

µA typ µA max V min/max

Test Conditions/Comments

VS = ±4.5 V, IS = −10 mA; see Figure 26 VDD = ±4.5 V, VSS = ±4.5 V VS = ±4.5 V, IS = −10 mA VS = ±4.5 V, IS = −10 mA VDD = +5.5 V, VSS = −5.5 V VS = ±4.5 V, VD = ±4.5 V; see Figure 27 VS = ±4.5V, VD = ±4.5 V; see Figure 27 VS = VD = ±4.5 V; see Figure 28

VIN = VGND or VDD

RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 29 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 30 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 RL = 110 Ω, VS = 5 V p-p, f = 20 Hz to 20 kHz; see Figure 36 RL = 50 Ω, CL = 5 pF; see Figure 34 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V or VDD

ADG1633/ADG1634

Data Sheet

12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD

25°C

−40°C to +85°C

−40°C to +125°C 0 V to VDD

4 4.5 0.12 0.25 0.9 1.2 ±0.01 ±0.1 ±0.02 ±0.15 ±0.02 ±0.15

6.5

7.5

0.3

0.35

1.6

1.9

±1.5

±12

±2

±20

±2

±20 2.0 0.8

V min V max

±0.1

µA max pF typ

nA typ

8

−64 −64 0.3

ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ

109 19 32 56


182

205

43

47

180

200 30

Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) −3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD

−12.4

0.001 1.0

TSSOP

300 480

LFCSP VDD 1

V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max

±1

127 151 31 38 128 152 45

Unit

375 600 3.3/16

Guaranteed by design, but not subject to production test.


µA typ µA max µA typ µA max µA typ µA max V min/max


VS = 0 V to 10 V, IS = −10 mA; see Figure 26 VDD = 10.8 V, VSS = 0 V VS = 10 V, IS = −10 mA VS = 0 V to 10 V, IS = −10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27 VS = VD = 1 V or 10 V; see Figure 28

VIN = VGND or VDD

RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 29 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 30 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 RL = 110 Ω, VS = 5 V p-p, f = 20 Hz to 20 kHz; see Figure 36 RL = 50 Ω, CL = 5 pF; see Figure 34 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 12 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 5 V

Data Sheet

ADG1633/ADG1634

5 V SINGLE SUPPLY VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH

25°C

−40°C to +85°C

−40°C to +125°C 0 V to VDD

8.5 10 0.15 0.3 1.7 2.3 ±0.01 ±0.1 ±0.02 ±0.15 ±0.02 ±0.15

12.5

14

0.35

0.4

2.7

3

±1.5

±12

±2

±20

±2

±20 2.0 0.8

±1 ±0.1


8

V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max nA typ µA max pF typ


199 254 68 90 201 256 57

Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N)

−5 −64 −64 0.27

ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ

104 21 37 62


tON (EN) tOFF (EN)

303

337

102

110

300

333 37

−3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD VDD 1

Unit

0.001 1.0 3.3/16





VS = 0 V to 4.5 V, IS = −10 mA; see Figure 26 VDD = 4.5 V, VSS = 0 V VS = 0 V to 4.5 V, IS = −10 mA VS = 0 V to 4.5 V, IS = −10 mA VDD = 5.5 V, VSS = 0 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 27 VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 27 VS = VD = 1 V or 4.5 V; see Figure 28

VIN = VGND or VDD

RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 29 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 30 VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 33 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 35 RL = 110 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p; see Figure 36 RL = 50 Ω, CL = 5 pF; see Figure 34 VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VDD = 5.5 V Digital inputs = 0 V or VDD

ADG1633/ADG1634

Data Sheet

3.3 V SINGLE SUPPLY VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON)

25°C

−40°C to +85°C

−40°C to +125°C

Unit

13.5

15

0 V to VDD 16.5

V Ω typ

On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off )

0.25 5

0.28 5.5

0.3 6.5

Ω typ Ω typ

±1.5

±12

±2

±20

±2

±20

Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH

±0.01 ±0.1 ±0.01 ±0.15 ±0.01 ±0.15

2.0 0.8 ±1 ±0.1


8

V min V max nA typ µA max pF typ


309 429 132 184 313 416 81

Charge Injection Off Isolation

−10 −64

ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ

Channel-to-Channel Crosstalk

−64

dB typ

Total Harmonic Distortion + Noise (THD + N)

0.6

% typ

117 22 39 64


tON (EN) tOFF (EN)

466

508

201

210

470

509 48

−3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD VDD 1

nA typ nA max nA typ nA max nA typ nA max

0.001 1.0 3.3/16





VS = 0 V to VDD, IS = −10 mA; see Figure 26, VDD = 3.3 V, VSS = 0 V VS = 0 V to VDD, IS = −10 mA VS = 0 V to VDD, IS = −10 mA VDD = 3.6 V, VSS = 0 V VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 27 VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 27 VS = VD = 0.6 V or 3 V; see Figure 28

VIN = VGND or VDD

RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 29 RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 31 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 30 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 33 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 35 RL = 110 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p; see Figure 36 RL = 50 Ω, CL = 5 pF; see Figure 34 VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VDD = 3.6 V Digital inputs = 0 V or VDD

Data Sheet

ADG1633/ADG1634

CONTINUOUS CURRENT PER CHANNEL, S OR D Table 5. ADG1633 Parameter CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = −5 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) VDD = 5 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W) VDD = 3.3 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 48.7°C/W)

25°C

85°C

125°C

Unit

126 206

84 126

56 70

mA max mA max

133 213

87 133

56 73

mA max mA max

98 157

70 105

45 63

mA max mA max

77 129

56 87

38 56

mA max mA max

25°C

85°C

125°C

Unit

112 220

77 136

52 73

mA max mA max

119 234

80 140

52 73

mA max mA max

87 171

63 112

42 66

mA max mA max

70 140

52 94

35 59

mA max mA max

Table 6. ADG1634 Parameter CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = −5 V TSSOP (θJA = 95°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 95°C/W) LFCSP (θJA = 30.4°C/W) VDD = 5 V, VSS = 0 V TSSOP (θJA = 95°C/W) LFCSP (θJA = 30.4°C/W) VDD = 3.3 V, VSS = 0 V TSSOP (θJA = 95°C/W) LFCSP (θJA = 30.4°C/W)


ADG1633/ADG1634

Data Sheet

ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D Continuous Current, S or D 2 Operating Temperature Range Industrial (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance, 0 Airflow (4Layer Board) 20-Lead TSSOP, θJA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP (3 mm × 3 mm), θJA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP (4 mm × 4 mm), θJA Thermal Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak Temperature, Pb free

Rating 18 V −0.3 V to +18 V +0.3 V to −18 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 450 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15%

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

−40°C to +125°C −65°C to +150°C 150°C 112.6°C/W 95°C/W 48.7°C/W 30.4°C/W 260°C

Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. 2 See Table 5 and Table 6. 1


Data Sheet

ADG1633/ADG1634

10 S3B

9

IN3

08319-004

10 S3A

8

13 IN1

TOP VIEW (Not to Scale)

9

D2 4

11 D3

D2 6 S2A 7 IN2

S2B 3

D3

NOTES 1. EXPOSED PAD IS TIED TO THE SUBSTRATE, VSS.

Figure 4. ADG1633 TSSOP Pin Configuration

08319-005

12 S3B

11 VSS

IN3 7

S2B 5


AD1633

S3A 8

13 VSS

S1B 2

S2A 5

ADG1633

12 EN

D1 1

14 EN

D1 3 S1B 4

14 GND

16 S1A 16 GND 15 IN1

IN2 6

VDD 1 S1A 2

15 VDD

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. ADG1633 LFCSP Pin Configuration

Table 8. ADG1633 Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 2 16 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12

Mnemonic VDD S1A D1 S1B S2B D2 S2A IN2 IN3 S3A D3 S3B VSS EN

15 16 N/A

IN1 GND EP

13 14 17

Description Most Positive Power Supply Potential. Source Terminal 1A. Can be an input or an output. Drain Terminal 1. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Drain Terminal 2. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Logic Control Input 2. Logic Control Input 3. Source Terminal 3A. Can be an input or an output. Drain Terminal 3. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Active Low Digital Input. When this pin is high, the device is disabled and all switches are off. When this pin is low, INx logic inputs determine the on switches. Logic Control Input 1. Ground (0 V) Reference. Exposed Pad. The exposed pad is tied to the substrate, VSS.

Table 9. ADG1633 Truth Table EN 1 0 0 1

INx X1 0 1

SxA Off Off On

SxB Off On Off

X = don’t care.


18

D4

S1B 4

17

S4B VDD

VSS 5

ADG1634

16

GND 6


15

NC

14

S3B

S2B 7

13

D3

12

S3A

IN2 10

11

IN3 08319-006

D2 8 S2A 9

D1 1 S1B 2 VSS 3 GND 4 S2B 5

NC = NO CONNECT

ADG1634 TOP VIEW (Not to Scale)

15 14 13 12 11

D4 S4B VDD S3B D3

NOTES 1. EXPOSED PAD IS TIED TO THE SUBSTRATE, VSS.

08319-007

S4A

D1 3

S1A

20 19 18 17 16

IN4

19

6 7 8 9 10

20

2

D2 S2A IN2 IN3 S3A

IN1 1

Data Sheet S1A IN1 EN IN4 S4A

ADG1633/ADG1634

Figure 7. ADG1634 LFCSP Pin Configuration

Figure 6. ADG1634 TSSOP Pin Configuration

Table 10. ADG1634 Pin Function Descriptions Pin No. TSSOP LFCSP 1 19 2 20 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12 15 N/A 16 13 17 14 18 15 19 16 20 17 N/A 18

Mnemonic IN1 S1A D1 S1B VSS GND S2B D2 S2A IN2 IN3 S3A D3 S3B NC VDD S4B D4 S4A IN4 EN

N/A

EP

21

Description Logic Control Input 1. Source Terminal 1A. Can be an input or an output. Drain Terminal 1. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Ground (0 V) Reference. Source Terminal 2B. Can be an input or an output. Drain Terminal 2. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Logic Control Input 2. Logic Control Input 3. Source Terminal 3A. Can be an input or an output. Drain Terminal 3. Can be an input or an output. Source Terminal 3B. Can be an input or an output. No Connect. Most Positive Power Supply Potential. Source Terminal 4B. Can be an input or an output. Drain Terminal 4. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Logic Control Input 4. Active Low Digital Input. When this pin is high, the device is disabled and all switches are off. When this pin is low, INx logic inputs determine the on switches. Exposed Pad. The exposed pad is tied to the substrate, VSS.

Table 11. ADG1634 TSSOP Truth Table INx 0 1

SxA Off On

SxB On Off

SxA Off Off On

SxB Off On Off

Table 12. ADG1634 LFCSP Truth Table EN 1 0 0 1

INx X1 0 1

X = don’t care. Rev. B | Page 10 of 19

Data Sheet

ADG1633/ADG1634

TYPICAL PERFORMANCE CHARACTERISTICS 7

7 VDD = 12V VSS = 0V

TA = 25°C

6

5 VDD = +3.3V VSS = –3.3V

4

3

VDD = +5V VSS = –5V

2


5

ON RESISTANCE (Ω)

TA = +125°C

4

TA = +85°C TA = +25°C

3

TA = –40°C

2

1

–8

–4

–6

–2

0

4

2

6

8

SOURCE OR DRAIN VOLTAGE (V)

0

08319-029

0

2

0

4

6

Figure 8. On Resistance vs. VD (VS), Dual Supply

12

10

Figure 11. On Resistance vs. VD (VS) for Different Temperatures, 12 V Single Supply

16

12

TA = 25°C

VDD = 3.3V VSS = 0V

14

10 TA = +125°C

ON RESISTANCE (Ω)

12

ON RESISTANCE (Ω)

8


08319-032

1

10 VDD = 5V VSS = 0V

8 6

VDD = 16V VSS = 0V

VDD = 12V VSS = 0V

4

TA = +85°C

8

TA = +25°C

6

TA = –40°C

4

2

2

VDD = 5V VSS = 0V

0

2

6

4

8

12

10

14

16


0

08319-030

0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0


Figure 9. On Resistance vs. VD (VS), Single Supply

08319-033

ON RESISTANCE (Ω)

6

Figure 12. On Resistance vs. VD (VS) for Different Temperatures, 5 V Single Supply

7

18


VDD = 3.3V VSS = 0V

16

6

ON RESISTANCE (Ω)

TA = +85°C 4 TA = +25°C 3

TA = –40°C

2

12

TA = +125°C TA = +85°C TA = +25°C TA = –40°C

10 8 6 4

1

–4

–3

–2

–1

0

1

2

3

4

5


Figure 10. On Resistance vs. VD (VS) for Different Temperatures, ±5 V Dual Supply

0 0

0.5

1.0

1.5

2.0

2.5

3.0


Figure 13. On Resistance vs. VD (VS) for Different Temperatures, 3.3 V Single Supply


08319-021

0 –5

2 08319-031

ON RESISTANCE (Ω)

14

TA = +125°C

5

ADG1633/ADG1634

Data Sheet

12

10 VDD = +5V VSS = –5V VBIAS = +4.5V/–4.5V

8

6 4

LEAKAGE CURRENT (nA)

ID (OFF) – + ID, IS (ON) + + IS (OFF) + –

2 0 –2 ID, IS (ON) – – IS (OFF) – + ID (OFF) + –

–4 –6 40

60

80

100

4

2

0

–8 20

120

TEMPERATURE (°C)

–2 0

20

80

60

120

100

Figure 17. ADG1633 Leakage Currents vs. Temperature, 3.3 V Single Supply

15

600

VDD = 12V VSS = 0V VBIAS = 1V/10V

IDD PER CHANNEL TA = 25°C IDD = +12V ISS = 0V

500

10 ID, IS (ON) + + ID (OFF) – + IS (OFF) + –

400

IDD (µA)

300 IDD = +5V ISS = –5V

0 200

IDD = +5V ISS = 0V

ID, IS (ON) – – IS (OFF) – + ID (OFF) + –

20

40

60

80

100

120

TEMPERATURE (°C)

0

08319-034

–10 0

IDD = +3.3V ISS = 0V

100

0

2

4

6

8

10

12

14

LOGIC (V)

08319-020

5

–5

Figure 18. IDD vs. Logic Level

Figure 15. ADG1633 Leakage Currents vs. Temperature, 12 V Single Supply 100

10 VDD = 5V VSS = 0V VBIAS = 1V/4.5V

8

80

6

CHARGE INJECTION (pC)

60

ID, IS (ON) + + ID (OFF) – + ID (OFF) + – IS (OFF) + – IS (OFF) – + ID, IS (ON) – –

4

2


40

VDD = +5V VSS = 0V

20 VDD = +3.3V VSS = 0V

0

VDD = +12V VSS = 0V

–20 –40 –60 –80

0

–2 0

20

40

60

80

100

120

TEMPERATURE (°C)

–120 –6

–4

–2

0

2

4

6

8

10

12

VS (V)

Figure 16. ADG1633 Leakage Currents vs. Temperature, 5 V Single Supply

Figure 19. Charge Injection vs. Source Voltage


14

08319-027

–100 08319-036


40

TEMPERATURE (°C)

Figure 14. ADG1633 Leakage Currents vs. Temperature, ±5 V Dual Supply


ID, IS (ON) + + ID, IS (ON) – – ID (OFF) – + IS (OFF) + – ID (OFF) + – IS (OFF) – +

6

08319-035


8

0

VDD = 3.3V VSS = 0V VBIAS = 0.6V/3V

08319-019

10

Data Sheet

ADG1633/ADG1634

350

0 TA = 25°C VDD = +5V VSS = –5V

TA = 25°C VDD = +3.3V, VSS = 0V VDD = +5V, VSS = 0V VDD = +5V, VSS = –5V VDD = +12V, VSS = 0V

250

–1

INSERTION LOSS (dB)

200

150

100

–2

–3

–4

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

–6 10k

08319-025

0 –40

0.7 TA = 25°C VDD = +5V VSS = –5V

100M

1G

LOAD = 110Ω TA = 25°C

0.6

VDD = +3.3V, VS = 2V p-p

–20

0.5 –30

THD + N (%)

–40 –50

0.4

0.3

VDD = +5V, VS = 3.5V p-p

–60

0.2 –70

VDD = +5V, VSS = –5V, VS = 5V p-p 0.1

–80

100k

1M

10M

100M

1G

FREQUENCY (Hz)

0

08319-023

–90 10k

VDD = +12V, VS = 5V p-p

0

5k

–10

15k

20k

Figure 24. THD + N vs. Frequency

Figure 21. Off Isolation vs. Frequency

0

10k FREQUENCY (Hz)

08319-028

OFF ISOLATION (dB)

10M

Figure 23. On Response vs. Frequency

0

0

TA = 25°C VDD = +5V VSS = –5V

–20

TA = 25°C VDD = +5V VSS = –5V NO DECOUPLING CAPACITORS

–20 –40

ACPSRR (dB)

–30 –40 –50

–60

–80

–60

DECOUPLING CAPACITORS

–70 –100

–80 –90 10k

100k

1M

10M

100M

FREQUENCY (Hz)

1G

08319-024

CROSSTALK (dB)

1M

FREQUENCY (Hz)

Figure 20. Transition Time vs. Temperature

–10

100k

08319-022

–5

50

–120 1k

10k

100k

1M

FREQUENCY (Hz)

Figure 25. ACPSRR vs. Frequency

Figure 22. Crosstalk vs. Frequency


10M

100M

08319-026

TRANSITION TIME (ns)

300

ADG1633/ADG1634

Data Sheet

TEST CIRCUITS S

D

IDS RON = V ÷ IDS

Figure 27. Off Leakage

ID (ON)

S1

NC

D S2

VS

A

08319-010

VD

Figure 28. On Leakage

VDD

VSS

VDD

VIN

50%

50%

VIN

50%

50%

VSS

SB

VS

0.1µF

D

SA

VOUT RL 100Ω

IN

CL 35pF

90%

90%

VOUT

tON

tOFF

08319-011

GND

VIN

Figure 29. Switching Timing

0.1µF

VDD

VSS

VDD

VSS

SB

VS

0.1µF VIN

D

SA

VOUT RL 100Ω

IN

VOUT 80%

CL 35pF

tBBM

GND

tBBM 08319-012

VIN

Figure 30. Break-Before-Make Delay, tD

VDD

VSS

VDD

VSS

0.1µF 3V ENABLE DRIVE (VIN)

ADG1633 INx

S1A

INx

S1B

VS

VOUT

INx

VIN

50Ω

VOUT

D1

EN GND

50%

50%

0V

RL 100Ω

CL 35pF

OUTPUT 0V

Figure 31. Enable Delay, tON (EN), tOFF (EN) Rev. B | Page 14 of 19

tOFF (EN) 0.9VOUT

tON (EN)

0.9VOUT 08319-013

0.1µF

A

VD

VS

Figure 26. On Resistance

0.1µF

ID (OFF)

SB

A

D

08319-008

VS

SA

A

08319-009

IS (OFF)

V

Data Sheet

ADG1633/ADG1634

VS

VDD

VSS

VDD

VSS

0.1µF VIN (NORMALLY CLOSED SWITCH)

SB

D

NC

SA CL 1nF

IN

VOUT

OFF

VIN (NORMALLY OPEN SWITCH) VOUT

GND

VIN

ON

∆VOUT

QINJ = CL × ∆VOUT

08319-014

0.1µF

Figure 32. Charge Injection

VDD VDD

VSS SA

NETWORK ANALYZER

NETWORK ANALYZER NC

SB

VOUT

VDD SA

RL 50Ω

50Ω

D SB

50Ω VS

D

VIN

OFF ISOLATION = 20 log

VOUT VS

GND

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

Figure 33. Off Isolation

R 50Ω

IN

VS

VOUT

08319-015

RL 50Ω

GND

VDD

VSS

VOUT VS

08319-017

VDD

Figure 35. Channel-to-Channel Crosstalk

VSS 0.1µF VDD

VDD

VSS SA

NC

VSS 0.1µF

0.1µF

NETWORK ANALYZER

AUDIO PRECISION

50Ω VDD

SB VS

RL 50Ω

GND

VS V p-p

IN

VOUT

D VIN

VOUT WITH SWITCH VOUT WITHOUT SWITCH

RL 110Ω

08319-016

GND

INSERTION LOSS = 20 log

RS

S

D VIN

VSS

Figure 36. THD + Noise

Figure 34. Bandwidth


VOUT 08319-018

0.1µF

IN

0.1µF

0.1µF

0.1µF

IN

VSS

0.1µF

VSS

ADG1633/ADG1634

Data Sheet

TERMINOLOGY tBBM Off time measured between the 80% point of both switches when switching from one address state to another.

RON Ohmic resistance between Terminal D and Terminal S. ∆RON The difference between the RON of any two channels. RFLAT(ON) The difference between the maximum and minimum value of on resistance measured.

VIL Maximum input voltage for Logic 0. VIH Minimum input voltage for Logic 1.

IS (Off) Source leakage current when the switch is off.

IIL (IIH) Input current of the digital input.

ID (Off) Drain leakage current when the switch is off.

IDD Positive supply current.

ID, IS (On) Channel leakage current when the switch is on.

ISS Negative supply current.

VD (VS) Analog voltage on Terminal D and Terminal S.

Off Isolation A measure of unwanted signal coupling through an off channel.

CS (Off) Channel input capacitance for off condition.

Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching.

CD (Off) Channel output capacitance for off condition.

Bandwidth The frequency at which the output is attenuated by 3 dB.

CD, CS (On) On switch capacitance.

On Response The frequency response of the on switch.

CIN Digital input capacitance.

Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental.

tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANS Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another.

AC Power Supply Rejection Ratio (ACPSRR) A measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.


Data Sheet

ADG1633/ADG1634

OUTLINE DIMENSIONS 5.10 5.00 4.90

16

9

4.50 4.40 4.30

6.40 BSC 1

8

PIN 1 1.20 MAX

0.15 0.05

0.20 0.09 0.30 0.19

0.65 BSC

COPLANARITY 0.10

0.75 0.60 0.45

8° 0°

SEATING PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters

0.30 0.23 0.18 0.50 BSC

13

PIN 1 INDICATOR

16 1

12 EXPOSED PAD

1.75 1.60 SQ 1.45

9

TOP VIEW 0.80 0.75 0.70 SEATING PLANE

0.50 0.40 0.30

4 8

5

0.25 MIN

BOTTOM VIEW

0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.

Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters


08-16-2010-E

PIN 1 INDICATOR

3.10 3.00 SQ 2.90

ADG1633/ADG1634

Data Sheet 6.60 6.50 6.40

20

11

4.50 4.40 4.30 6.40 BSC 1

10

PIN 1 0.65 BSC 1.20 MAX

0.15 0.05 COPLANARITY 0.10

0.30 0.19

0.20 0.09

0.75 0.60 0.45

8° 0°

SEATING PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 39. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters

PIN 1 INDICATOR

4.10 4.00 SQ 3.90

0.30 0.25 0.20 0.50 BSC

20

16 15

PIN 1 INDICATOR

1

EXPOSED PAD

2.65 2.50 SQ 2.35 5

11

0.80 0.75 0.70 SEATING PLANE

0.50 0.40 0.30

6

0.25 MIN

BOTTOM VIEW

0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-20-10) Dimensions shown in millimeters


061609-B

TOP VIEW

10

Data Sheet

ADG1633/ADG1634

ORDERING GUIDE Model 1 ADG1633BRUZ ADG1633BRUZ-REEL7 ADG1633BCPZ-REEL7 ADG1634BRUZ ADG1634BRUZ-REEL7 ADG1634BCPZ-REEL7 1

Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C

Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP]

Z = RoHS Compliant Part.

©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08319-0-8/16(B)


EN Pin Yes Yes Yes No No Yes

Package Option RU-16 RU-16 CP-16-22 RU-20 RU-20 CP-20-10

Branding

SD3

Quad SPDT ±5 V, +12 V, +5 V, and +3.3 V

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