Under the Hood of Flyback SMPS Designs PPT Presentation

Power Supply Design Seminar Topic 1 Presentation:

Under the Hood of Flyback SMPS Designs Reproduced from 2010 Texas Instruments Power Supply Design Seminar SEM1900, Topic 1 TI Literature Number: SLUP254 © 2010, 2011 Texas Instruments Incorporated

Power Seminar topics and online powertraining modules are available at: power.ti.com/seminars

Topic 1

Under the Hood of Flyback SMPS Designs

Jean Picard

SLUP254

Agenda 1. Basics of Flyback Topology 2 Impact of Transformer Design on Power Supply 2. Performance 3. Power Supply Current Limiting 4. Summary

Texas Instruments—2010 Power Supply Design Seminar

1-2 SLUP254

Transfer of Energy • FET turns ON – Voltage across primary magnetizing inductance ≅ Vi • E Energy iis stored t d in i flyback fl b k transformer: Function of L, D and Ts

– Secondary y diode in blocking g state

IP Io +Vi

1:n2

– During commutation: Leakage energy absorbed by clamp circuit – Stored energy transferred to output through diode – If DCM operation operation, all the stored energy is transferred

Cla amp

• FET turns OFF

IP

- + +

Vo Iout

Vdrain

• Pulsating input and output currentt Texas Instruments—2010 Power Supply Design Seminar

1-3 SLUP254

Transfer of Energy • FET turns ON – Voltage across primary magnetizing inductance ≅ Vi

• Energy is stored in flyback transformer: Function of L, D and Ts

IP Io

– Secondary diode in blocking state

+V Vi

– During commutation: Leakage energy absorbed by clamp circuit – Stored energy transferred to output through diode – If DCM operation operation, all the stored energy is transferred

Io

1:n2 Clam mp

• FET turns OFF

IP

+

-

Vo Iout

Vdrain

• Pulsating input and output currentt Texas Instruments—2010 Power Supply Design Seminar

1-4 SLUP254

Transfer of Energy • FET turns ON O – Voltage across primary magnetizing inductance ≅ Vi


IP Io


+Vi

– During commutation: Leakage energy absorbed by clamp circuit – Stored St d energy transferred t f d to t output through diode – If DCM operation, all the stored energy is transferred

1:n2 Clamp

• FET turns OFF O

Io

+

-

Vo Iout

Vdrain

• Pulsating input and output current


1-5 SLUP254

Transfer of Energy • FET turns ON – Voltage across primary magnetizing inductance ≅ Vi


+Vi

1:n2

• FET turns OFF – During commutation: Leakage energy absorbed by clamp circuit – Stored energy transferred to output through diode – If DCM operation, all the stored energ is transferred energy

Clamp


Vo Iout

Vdrain

• Pulsating input and output current


1-6 SLUP254

CCM versus DCM • Continuous conduction mode (CCM) – Small ripple and rms current – Lower MOSFET conduction and turn-off loss – Lower core loss – Lower capacitors loss – Can have better “full load” efficiency – Smaller S ll EMI and d output t t filters filt

• Discontinuous conduction mode (DCM) – No diode reverse recovery loss – Lower inductance value

• May result in a smaller transformer

– Better “no no load load” efficiency – First-order system

Vdrain Primary MOSFET Primary C Current IP Secondary Current Io

Vo n2 + Vi

Ipk

Ipkmin

ΔIL

ΔILS S

(1 – D) x Ts

m2S

Io_avg _ g Time (t) Ts

Vdrain Primary MOSFET

D × Ts

Vo n2 + Vi

Vi Ipk

Primary Current IP

(1 – D) × Ts Idle Period

• Inherently stable

– No RHPZ p problem – Slope compensation not needed in CMC

D x Ts

T

Secondary Current Io


Io_avg Time (t)

1-7 SLUP254

Right-Half-Plane Zero, CCM Operation Cllamp

– Effect of control action during ON time is delayed y until next switch turn OFF

– Phase decreases with increasing gain

f RPHZ =

(1 − D )

2

IP

-

+

Vo Iout

+

Vdrain

• Initial reaction is in opposite direction of desired correction ⇒ RHP Zero

1:n2

FET ON +Vi

× Vo

2πL × D × Iout × n 22

D ↔ Main M i switch it h d duty-cycle t l Texas Instruments—2010 Power Supply Design Seminar

1 2 1:n Clamp

• Energy is delivered during 1 – D

+Vi

Io

+

-

Vo Iout

Vdrain

FET OFF

1-8 SLUP254

RCD Clamp Circuit • During commutation primary-toprimary to secondary, the leakage energy is absorbed by the clamp circuit –

Rc la m p

+

– Rclamp dissipates the leakage energy and some magnetizing energy

+Vi

– The clamp capacitor ensures a low voltage ripple

Diode or Synchronous N1:N2 Rectifier Vc la m p IP Vdra in

– Use short connection with minimum loop area

• Vclamp is maximum at full load and minimum input voltage – Rclamp selected for a maximum drain voltage in worst case – Tradeoff between efficiency, peak drain voltage, output current limit and cross regulation (see ringing effect)

Vo

RS Clamp-Diode Forward Recovery Vi + Vc la m p Vdra in Primary MOSFET


Leakage-Inductance Demagnetization Vi +

Vo n

1-9 SLUP254

Agenda 1. Basics of Flyback Topology 2 Impact of Transformer Design on Power 2. Supply Performance 3. Power Supply Current Limiting 4. Summary


1-10 SLUP254

Transformer’s Leakage Inductance • Transformer’s Transformer s leakage inductance represented by Lleak2 – Primary winding is the closest to center gap

–

–

Vi

+

Clamp

Vmag1

+

+

IP

• Voltage spike on FET during commutation • Rate of rise of current is influenced byy leakage g inductance • Commutation primary-tosecondary is not instantaneous p on Vclamp and depends

Lm

+

+ Vleak2 –

Vmag2

IS

VD

–

During Primary-toSecondary Commutation

ø

+

Vout

–

W1

FET W2

• When FET turns OFF – Lleak2 opposes to IP decrease and IS increase – Magnetizing inductance works to maintain magnetizing current

Lleak2

N1:N2

Clamp Diode Forward Recovery

Leakage Inductance Demagnetization Current Circulates in Secondary y Winding(s) g( )

Vi + Vclamp

Vclamp

VFET

Leakage Inductance Resonates with Drain Capacitance

Vi + Vclamp

VFET

Cl Clamp C Capacitor it Voltage V lt

Vmag2

Clamp Capacitor Voltage

0V Vmag2 – VD – Vout

Vleak2

IP

Reduction in Magnetizing Current Due to Faster Commutation

IP

IS

IS Dtr

– Loss of volt-seconds

Lost Volt-Seconds

Low Clamp Voltage


Dtr

High Clamp Voltage

1-11 SLUP254

Effects of Leakage Inductance • Clamp circuits and snubbers needed for primary FET and secondary rectifier(s) • Lower power-supply efficiency • Impact p on g gate-drive strategy gy if synchronous y rectifier is used • Higher g duty y cycle y and magnetizing g g current than expected p • Higher H-field radiated emission • High Hi h iimpactt on cross-regulation l ti


1-12 SLUP254

How Leakage Can Be Minimized • Leakage inductance is a function of winding geometry geometry, number of turns and separation between primary and secondary – Minimize the separation between the primary and main secondary winding(s) – Interleave the primary and main secondary – Select a core with a long and narrow window L

L

W2 W1 W2 W1

W1 W2 W2 W1

W1 W2 W1 W2

W1 W2 W2 W1

Option 1

Option 2

• Leakage inductance is not lowered with a high permeability core • Having the winding tightly coupled to the core will not reduce it Texas Instruments—2010 Power Supply Design Seminar

1-13 SLUP254

Cross-Regulation – Overview • Multiple-output flyback topology is popular because of its simplicity and low cost • If the coupling is perfect, the turns ratio directly defines output voltages • In the real world, “perfect” coupling is not possible • This often results in poor cross-regulation


1-14 SLUP254

Cross-Regulation Physical Model • Transformer windings cannot all be equally well coupled to the gap because of physical separation between them • Magnetic energy stored between the windings represented as leakage inductances • Model not applicable to any transformer geometry •C Can b become complex l if iinterleaving t l i iis used, d or if multiple lti l secondary windings are wound simultaneously (multifilar) • Not accurate in situation of lightly loaded secondary outputs • Good tool to understand how the common flyback transformer geometries work Texas Instruments—2010 Power Supply Design Seminar

1-15 SLUP254

Cross-Regulation Physical Model lW4

+ Vi –

Clamp

+ V3 –

lW2

+ V2 –

+ N1:N2

W4 W

N3

W3 W

lp

W2 W

lW3

W1 W Primary

+ V4 –

N4

FET

Basic Flyback Circuit lp –

Vi

+

Clamp

+

Lleak12

Vmag1 Lm

Transformer Construction Lleak34

Lleak23

I2

I3

N2:N3 IW33

I4

N2:N4 IW4

N1:N2 FET

+ V2 –

+ V3 –

+ V4 –

Transformer Physical Model

• This circuit is only applicable to the transformer windings stackup shown • Each leakage inductance considered is between two consecutive secondaries • Also called “Ladder model” Texas Instruments—2010 Power Supply Design Seminar

1-16 SLUP254

Flux Lines during Commutation Each Secondary Winding with Nominal Load • φm decreases during commutation

φm

• dφ/dt (decreasing) in each secondary winding d g is s limited ted by its ts output voltage o tage – Increasing current induced in W2 to W4 to maintain φm in the gap

e = −N ×

W2

dφ m dt

W1

W3 W4

L

• Leakage between W2 and W1 – W1’s voltage limited by clamp

• W1 closest to gap

During Primary-to-Secondary Commutation Current in All Windings

– Vclamp limits dφm/dt in the gap during commutation

• W2 is next to W1

– W2 limits the dφ/dt seen by W3 and W4 – W3 and W4 output voltage lower than without leakage

• Current commutates progressively from near to remote secondary windings Texas Instruments—2010 Power Supply Design Seminar

lp

I2 I3 I4

Secondary Currents During C Commutation t ti Based B d on Physical Ph i l Model M d l

1-17 SLUP254

Ringing Effect • High Hi h dV/dt when h main i switch it h tturns off ff if main i output t t iis h heavily il lloaded d d • Transformer leakage inductance and parasitic capacity ⇒ auxiliary secondary y voltage g tends to “ring” g • If auxiliary output fully loaded ⇒ this ringing is clamped • If lightly loaded ⇒ voltage overshoot with peak detector effect • Much higher (sometimes > 2 x nominal value!) auxiliary output voltage at light load – Primary clamp voltage has high impact on result

• Most existing transformer models fail to predict this • This effect can be mitigated (but not eliminated) – Minimize leakage inductance between secondary windings – Locate the highest power secondary(ies) closest to the primary

• Other solutions include a post-regulator, series resistor or minimum load Texas Instruments—2010 Power Supply Design Seminar

1-18 SLUP254

Cross-Regulation Example Auxiliary Output Lightly Loaded • W2 (high current output) heavily loaded, W4 lightly loaded – W4’s output received too much energy gy during g Phase 1 due to ringing – W2’s output did not receive enough energy

• At end of commutation ((Phase 1): ) – Σ{reflected secondary currents} Ù magnetizing current

• V4 went too high g – Phase 2: high dφ/dt (decreasing) in W4 • IW4 ⇒ 0 A rapidly

– IW2 increases to maintain φm in the gap

• After IW4 crosses 0 A, W2’s and W3’s di/dt change to maintain the downslope of the magnetizing current and flux

φm H×δ = ×δ = ∑ N×I A×μ


I4_pk IW4 I3_pk

IW3

Effect of V3 Capacitors ESR

V3 I2_pk IW2 Vmag1 IP_pk

IP Phase 1

Phase 2

Phase 3

Time (t)

φm W2 W1

W3 W4

Phase 2: No Primary Current

1-19 SLUP254

Test Results 10 Ω R W3

VD D

VAW3

W3 ( 9T)

W4 ( 14T)

300 Ω

W4 W3 W6

W2

36 Ω

W1B

W6 (9T)

V6 R6

6.8 µF

Current Probe IW4

Current Transformer V Iprim V_I 100 1 100:1

W1A

Current Probe IW6

V4 6.8 µF

+Vi

R c la m p 15 kΩ

0.1 µF

Vc la m p MURS120

5V W1 ( 21T) IP

W2 ( 4T) IW2

Primary MOSFET

• Input voltage: 48 V

Current Transformer 1:100 V_Is e c 6.8 Ω 249 Ω

I5

To CS Input

V

To 5-V Filter and Load

Sync Rectifier

• 5-V 5 V output t t load: l d 0 A to t 5A • Auxiliary outputs: V6 ((10 V at 0 to 140 mA)) and V4 (18 V at 0 to 200 mA)

R4

• Switching frequency: 250 kHz • Primary magnetizing inductance: 70 µH


1-20 SLUP254

Cross-Regulation Test Results with p Fully y Loaded Main Output IW6 (0.5 A/div) 2

IW4 (1 A/div)

IW6 (0.5 A/div) 2

IW4 (1 A/div)

4

4

IW2 (2.94 A/div)

IW2 (2.94 A/div) 1

1

Time (0.5 µs/div)

Time (0.5 µs/div)

V6 at 1 1.6 6W W, V4 at 2 2.5 5W W, I5 V = 5 A

V6 at 0 0.5 5W W, V4 at 3 3.6 6W W, I5 V = 5 A

• The two auxiliary outputs operate in DCM • Notice the change of slope of IW2 when IW4 or IW6 crosses 0 A Texas Instruments—2010 Power Supply Design Seminar

1-21 SLUP254

Cross-Regulation Test Results: Lightly Loaded Auxiliary y with Main Output p Fully y Loaded I5 V = 5 A, V4 at 0.3 W, Vclamp = 70 V

V6 (10 V/div)

12.4 V

I5 V = 5 A, V4 at 0.3 W, Vclampp = 70 V

V6 (10 V/div)

20.6 V

VW6 (10 V/div) V/di )

VW6 (10 V/div)

IW6 (200 mA/div)

Time ((1 µ µs/div))

V6 at 0.5 W

Time ((1 µ µs/div))

V6 at < 5 mW

• At minimum load, load V6 (10 V nominal) goes up to 20.6 20 6 V Texas Instruments—2010 Power Supply Design Seminar

1-22 SLUP254

Cross-Regulation Test Results with Main Output Fully Loaded : Impact of Clamp Voltage I5 V = 5 A, V4 at 0.3 W, Vclamp = 83 V

V6 (10 V/div)

14.4 V

I5 V = 5 A, V4 at 0.3 W,

V6 (10 V/div)

26 V

Vclamp = 83 V l

VW6 (10 V/div) V/di )

VW6 (10 V/div)

IW6 (200 mA/div)

Time (1 µs/div)

Time (1 µs/div)

V6 at 0.5 W

V6 at < 5 mW

• RCD resistor has been increased for higher Vclamp: 70 V ⇒ 83 V ⇒V6 increased significantly in both cases Texas Instruments—2010 Power Supply Design Seminar

1-23 SLUP254

Overload Test at Auxiliary Output: p of Leakage g Impact • There was no hiccup mode even at more than 3 A! • Th The overloaded l d d winding i di is unable to take all the energy because of leakage W3 having in leakage, fact a better coupling to primary than W6

IW4 (1 A/div)

I5 V = 0 A, V4 at 2.5 W, R6 = 1 Ω

4

3

VAW3 (20 V/div)

IW6 (2 A/div)

6.2-A Peak

2

– Enough energy delivered by W3 to VDD to maintain switching


Time (0.5 µs/div)

1-24 SLUP254

Benefits of Good Cross-Regulation • Good control of auxiliary outputs in spite of load variations • Better control of gate drive voltage amplitude, amplitude less gate drive losses • Lower rms current in output capacitors, lower dissipation • May allow the controller to reach hiccup mode more easily when the main output is short-circuited for better protection – Not necessarily true if the short-circuit is applied to an auxiliary output!


1-25 SLUP254

How Cross-Regulation can be Improved • The high current winding must have the best coupling to primary • Minimize leakage between all secondary windings • Optimize, p , not minimize,, the leakage g inductance of auxiliaryy windings g to p primary y • Use winding placement to control leakage inductance

W3

Primary B

W2B

W2A

Primary A

Primary B

W2B

W3

W2A

Primary A

W3

W2B

Primary B

W2A

Primary A

– Winding stackup – Spread each winding over the full width of the bobbin for better coupling If W3 is lightly loaded and W2 Better or is the highthan current main output.

• Operate main output in CCM • Try to avoid operating the auxiliary outputs in DCM. In some cases, consider using resistance in series with the diode • Consider winding more than one auxiliary secondary simultaneously (multifilar) • Lower clamp voltage may help

– Trade-off between cross regulation, efficiency, peak drain voltage and current limit – Some other types of clamp circuits may provide better results than the RCD clamp


1-26 SLUP254

Impact of Transformer Design on Flyback Efficiency

• Multifilar or Litz wires when necessaryy • Interleaving • Select core shape for minimum number of layers

– Optimize the transformer turns ratio for best efficiency – Select CCM operation

300

275 250

Secondary RMS Current Squared at 48 V

225 200 175

200

Good Duty-Cycle Trade-Off with 48-V Input p

150 125

100

100 75 50

20 x Primary RMS Current Squared at 48 V

25 0

0

20

40 60 Duty Cycle ( %)

80

2 Secondary RMS S Curr ent Squared d (A )

– Minimize leakage inductance from primary to main (high (high-current) current) secondary – Minimize transformer high frequency conduction loss

20x Primar y RM MS Current Squared d (A2)

• Th The following f ll i guidelines id li can be b used d during d i ttransformer f design to optimize the converter efficiency 300

0 100

• Other factors also have an indirect impact on efficiency – Cross-regulation

• VDD rail used for gate drive • Output capacitors rms current

– Impact of fringing flux from gap • Worse with planar transformers


1-27 SLUP254

Flyback and EMI IS

IP N1:N2

+

ICM

–

–

+

+Vi

Prim mary A

– Shields Vdrain E-field – Reduces R d iinterwinding t i di capacity it effect ff t on CE

• Minimize leakage for low H-field RE

• Center-gap transformer Texas Instruments—2010 Power Supply Design Seminar

+

Output to Chassis CM

• Better to start with end connected to primary MOSFET

• Interleaving reduces H-field RE but may increase effective ff ti P P-S S iinterwinding t i di capacitance it

Vout VD

FET

2

– Less if facing windings indings at same AC potential – Diode versus synchronous rectifier – Flyback ≠ Forward

Clamp

Other Secondary y

• Transformer and diode configuration impact effective capacitance

IDM

Secon ndary B

Vi

–

S

Secon ndary A

• Interwinding capacitance ⇒ CM CE

P

Prim mary C

– Use low Z caps, minimize loop areas – Output filter often required

ICM 2

Prim mary B

• Flyback ⇒ IP and IS pulsate

–

FET VD

Vout

+

1-28 SLUP254

Agenda 1. Basics of Flyback Topology 2 Impact of Transformer Design on Power Supply 2. Performance 3. Power Supply Current Limiting 4. Summary


1-29 SLUP254

Power Supply Current Limiting – Overview • Current-limiting characteristic of power supply defines: – Output power beyond which output voltage falls out of regulation. Corresponds to the “output load-current li it” (Iout_LIM) limit” – Output current in overload situations • including short-circuits short circuits

• Current-limiting characteristic is influenced by parasitics – Turn-off delays, leakage inductance,…


1-30 SLUP254

Understanding Current Limit – Flyback Power Supply with Peak CMC in CCM +Vi

Power Supply Controller –

PWM COMP ((From Error Amp)

+

VC _ LIM

Vo Iout

Primary Current

D x Ts

RSC

Secondary Current

R

I_SENSE VC

Io

Clamp

Slope Comp

Clock Ramp

1:n2

C

Rs

ΔIL

IA _LIM

Ipk_LIM

m2S

I o_avg

(1 – D) x Ts Time (t)

Just at Current Limit, Output Begins to Fall Out of Regulation

CurrentSense Filter

• Ipk_LIM is i th the primary i peak k current limit • Io_avg p current o avg is the output • If short-circuit, Io_avg can be much higher than when current limit has just been reached

Ipk_LIM

Primary Current

D x Ts

Secondary Current

I o_avg (1 – D) x Ts Time (t)

Output Short Circuit

Iout = Io _ avg =


IA × (1 − D ) n2 1-31 SLUP254

Current-Limit Model – Basic Representation • Peak CMC in CCM, fixed switching frequency I pk =

m2 m1

ΔIL

VC RS

IA (Average Magnetizing Current))

D × Ts Gate Control

Neglecting DC voltage drops:

Vo ΔI L ≈ m2 = (1 − D ) × TS n 2 × L Texas Instruments—2010 Power Supply Design Seminar

Vo D= n 2 × Vi + Vo 1-32 SLUP254

Influence of Input DC Voltage on Output Load Current Limit – Impact of Feedforward

Power Supply Controller

PWM COMP (From Error Amp)

+

Io

10

Vo Iout

Clamp

Slope Comp

Clock Ramp

–

1:n2

RSC R

I_SENSE VC

C

Rs

VC _ LIM

Output Loa ad Current L imit (A)

+Vi

Rff Feedforward

If Vi ↑ ⇒ (1 – D) ↑ ⇒ Iout_LIM increases

9

Without Feedforward

8 7 With Feedforward

6 5

20

25

30

35 40 45 Input Voltage(V)

50

55

• With feedforward, output load current limit becomes almost independent of input voltage ⇒ Better control during overload, less stress on power circuitry ⇒ Power limit ⇒ Cost C t and/or d/ size i reduction d ti • Feedforward also improves line noise rejection Texas Instruments—2010 Power Supply Design Seminar

1-33 SLUP254

Current Limit Model – With Feedforward VC K ff × V i

R S × I pk

RS × m 2 RS × g g Magnetizing Current)

RS × m1

RS × I A


• Kff x Vi is the feedforward contribution

– Subtracting it from Vc is identical to adding it to current feedback


1-34 SLUP254

Current Limit Model – Adding Slope Compensation Slope Compensation (Clock Ramp) – m0 x(Ts Tdis) 2

m0

K ff × V i

VC

RS × I A RS × m2

RS × IL_ pk m in D × Ts 2

R S × m1 Tdis


• Slope compensation to avoid subharmonic oscillation at duty-cycle duty cycle close to or higher than 50% • For easier understanding, slope compensation contribution subtracted from Vc. – Equivalent to slope compensation added to current feedback – In that circuit representation, the slope compensation is capacitively-coupled


1-35 SLUP254

Current Limit Model – With all Delays, Slope Compensation p and Feedforward • For a more accurate, parasitics must be included in the analysis • Parasitic delays – RC filter time delay – Turn off delay, including current comparator and gate drive – FET turn-on delay from onset of slope compensation ramp

• See Topic 1, Appendix A, in the Seminar Manual for detailed equations


1-36 SLUP254

Influence of Transformer Leakage on Output p Load Current Limit • Rate of rise of current is influenced by leakage, commutation primary-tosecondary is not instantaneous ⇒ Loss of volt-seconds (also influenced by the clamp voltage) ⇒ Duty-cycle and average magnetizing current have to increase to maintain the output voltage g conduction loss ⇒ Higher ⇒ Higher transformer peak current than expected -> Iout_LIM lower than expected

• Leakage inductance helps however to keep control of the output current in output short-circuit situation

–

Vi

+

Clamp

–

Ideal Xfmr Lleak2 N1:N2 + Vleak2 –

+

–

Vmag1

+

IP

Lm

Vmag2

VD

+ Vout

–

FET

IP IS

Lost Volt-Seconds

Vi × D new ≈ Vclamp × D tr +


+

IS

Dtr

Vo × (1 − D new − D tr ) n2 1-37 SLUP254

Current Limit During Overload – Example with Combined Effects

– Short-circuit: output current much higher than at onset of current limit

• Parasitic turn off delays may result in an out of control current if volt-seconds balance is not possible at the transformer – Transformer’s leakage i d t inductance h helps l tto maintain i t i that balance – If no leakage, the imbalance occurs starting g at Vo1 – With leakage, the imbalance occurs only from Vo2

Assuming no hiccup mode

25

Outpu ut Current (A)

• In overload: Output current increases ⇒ output voltage decreases

20

Without Leakage With Leakage

15

10

5

5

4.5

Vo _ short n2


4

(

3.5

3 2.5 2 1.5 Output Voltage (V)

1

0.5 0 Vo1 Vo2 Short Circuit

)

× TS − t del _ OFF − D tr × TS = Vi × t del × D tr × TS d l _ OFF − Vclamp l 1-38 SLUP254

Summary • Th The flflyback b k power ttransformer f iis th the kkey element l t off th the converter, for optimum efficiency and cross-regulation • Parasitics ha have e a strong infl influence ence on flflyback back con converter’s erter’s behavior, particularly under overload or short-circuit conditions • The primary clamp circuit design is a trade-off between: – – – –

Efficiency Peak drain voltage Output current limit Cross regulation Cross-regulation

• Simple feedforward technique can be used to optimize the converter and the system, lowering worst-case worst case components stress and reducing the overall cost and size Texas Instruments—2010 Power Supply Design Seminar

1-39 SLUP254

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SLUP254

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